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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Resending as the cc list was messed up. Hi, Apple's A10(X), T2 SoCs consists of pairs of performance and efficiency cores. However, only one of the core types may be active at a given time, and to software, it appears as logical cores that could switch between P-mode and E-mode, depending on the p-state. Unforunately, only the performance cores can execute 32-bit EL0. To software, this results in logical cores that lose ability to execute 32-bit EL0 when the p-state is below a certain value. Since these CPU cores only supported 16K pages, many AArch32 executables will not run anyways. This series disables 32-bit EL0 for these SoCs. Nick Chan --- Nick Chan (2): arm64: cputype: Add CPU types for A7-A11, T2 SoCs arm64: cpufeature: Pretend that Apple A10(X), T2 does not support 32-bit EL0 arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++--------- arch/arm64/kernel/cpufeature.c | 25 +++++++++++++++++++ 2 files changed, 55 insertions(+), 12 deletions(-) base-commit: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8