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SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240911_065159_695707_1CCD5269 X-CRM114-Status: GOOD ( 14.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series serves a few purposes: - Complete the S1PIE support to include EL2 - Sneak in the EL2 system register world switch As mentioned in few of the patches, this implementation relies on a very recent fix to the architecture (D22677 in [0]). * From v2 [2]: - Correctly reprogram the context for AT in the fast path when S1PIE is in use - Generalised sysreg RES0/RES1 masking, and added TCR2_EL2 RES0/RES1 bit handling - Fix TCR2_EL1, PIR_EL1, PIRE0_EL1 access with VHE - Add a bunch of missing registers to get_el2_to_el1_mapping() - Correctly map {TCR2,PIR,PIRE0}_EL2 to their EL1 equivalent on NV - Disable hierarchical permissions when S1PIE is enabled - Make EL2 world switch directly act on the vcpu rather than an arbitrary context - Remove SKL{0,1} from the TCR2_EL2 description * From the initial posting [1]: - Rebased on top of the AT support branch, which is currently sitting in kvmarm/next - Add handling for S1 indirect permission in AT, which I'm sure will give Alexandru another king-sized headache - Picked Mark Brown's series [3] dealing with TCRX and S1PIE visibility, and slapped an extra fix on top for good measure - Picked up RBs from Joey, with thanks. [0] https://developer.arm.com/documentation/102105/ka-04/ [1] https://lore.kernel.org/r/20240813144738.2048302-1-maz@kernel.org [2] https://lore.kernel.org/r/20240903153834.1909472-1-maz@kernel.org [3] https://lore.kernel.org/r/20240822-kvm-arm64-hide-pie-regs-v2-0-376624fa829c@kernel.org Marc Zyngier (21): arm64: Drop SKL0/SKL1 from TCR2_EL2 arm64: Remove VNCR definition for PIRE0_EL2 arm64: Add encoding for PIRE0_EL2 KVM: arm64: nv: Add missing EL2->EL1 mappings in get_el2_to_el1_mapping() KVM: arm64: nv: Handle CNTHCTL_EL2 specially KVM: arm64: nv: Save/Restore vEL2 sysregs KVM: arm64: Correctly access TCR2_EL1, PIR_EL1, PIRE0_EL1 with VHE KVM: arm64: Extend masking facility to arbitrary registers arm64: Define ID_AA64MMFR1_EL1.HAFDBS advertising FEAT_HAFT KVM: arm64: Add TCR2_EL2 to the sysreg arrays KVM: arm64: Sanitise TCR2_EL2 KVM: arm64: Add save/restore for TCR2_EL2 KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays KVM: arm64: Add save/restore for PIR{,E0}_EL2 KVM: arm64: Handle PIR{,E0}_EL2 traps KVM: arm64: Sanitise ID_AA64MMFR3_EL1 KVM: arm64: Add AT fast-path support for S1PIE KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts KVM: arm64: Disable hierarchical permissions when S1PIE is enabled KVM: arm64: Implement AT S1PIE support KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF Mark Brown (3): KVM: arm64: Define helper for EL2 registers with custom visibility KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests KVM: arm64: Hide S1PIE registers from userspace when disabled for guests arch/arm64/include/asm/kvm_host.h | 34 ++- arch/arm64/include/asm/vncr_mapping.h | 1 - arch/arm64/kvm/at.c | 322 +++++++++++++++++---- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 5 +- arch/arm64/kvm/hyp/nvhe/sysreg-sr.c | 2 +- arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 155 +++++++++- arch/arm64/kvm/nested.c | 34 ++- arch/arm64/kvm/sys_regs.c | 129 ++++++++- arch/arm64/tools/sysreg | 8 +- include/kvm/arm_arch_timer.h | 3 + 10 files changed, 597 insertions(+), 96 deletions(-)