From patchwork Mon Sep 23 10:06:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 13809472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB4C9CF9C6F for ; Mon, 23 Sep 2024 10:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=6su1T+DdHIoGvziFAdsvRRRDvDb+R7qafkVW7zFiJjo=; b=ZH0Z4HyuRaPYfd 9UBhQ1swoiI8vOyhh7eaLXI7AxfEq8u3uJh00taZMDJgLjAndAmCKZG5d3Lz5gGTXwXrHkum2CFKn PxX2+vJYK6mGJOXbm1FR7i0+LkQiiKfRlBpVApt8WJbKwJzY+kjg8CTlxASKewsbp5cDH6n3B78A+ lI9pKaBIVGbm9vEIqaiqMzR4ynO0spMdu8oFGSAgIz5dMo4EW5FSp6mdYAr6tx48f3iqfmSI21SkU qLunrJMgwrAYRKR6kcJJWRkSE0UivsR0EGM29ssk8ne9W4yYwG4ldwplu+TwaJBfV/AhU7CWO7w+I uG8KnBcz6P/z3MDf7oMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1ssfzP-0000000GvVR-3PiJ; Mon, 23 Sep 2024 10:08:19 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1ssfxO-0000000Gv0C-3yjP for linux-arm-kernel@lists.infradead.org; Mon, 23 Sep 2024 10:06:17 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 23 Sep 2024 18:06:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 23 Sep 2024 18:06:11 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v5 0/6] Add Aspeed G7 gpio support Date: Mon, 23 Sep 2024 18:06:05 +0800 Message-ID: <20240923100611.1597113-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240923_030615_013517_8C52A0A0 X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Aspeed 7th generation SoC features two GPIO controllers: one with 12 GPIO pins and another with 216 GPIO pins. The main difference from the previous generation is that the control logic has been updated to support per-pin control, allowing each pin to have its own 32-bit register for configuring value, direction, interrupt type, and more. This patch serial also add low-level operations (llops) to abstract the register access for GPIO registers and the coprocessor request/release in gpio-aspeed.c making it easier to extend the driver to support different hardware register layouts. Change since v4: - Add `reg_bank_get` callback - `reg_bits_get` -> `reg_bit_get - `dcache_require` -> `require_dcache` - Use `devm_clk_get_enabled` to get the clock source - g4 specific api doesn't need to use the callback function Change since v3: - Add `privilege_ctrl` and `privilege_init` callback - Use `bool aspeed_gpio_support_copro()` api to replace the `cmd_source_supoort` flag - Add the `dcache_require` flag and move the dcache usage into the reg_bit_set callback - `reg_bits_set` -> `reg_bit_set` and `reg_bits_read` -> `reg_bits_get` - `bool copro = 0` -> `bool copro = false` - `if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bits_get) return -EINVAL;` - Correct the access of reg_irq_status - Remove __init attribute to fix the compiler warning Change since v2: - Correct minItems for gpio-line names - Remove the example for ast2700, because it's the same as the AST2600 - Fix the sparse warning which is reported by the test robot - Remove the version and use the match data to replace it. - Add another two patches one for deferred probe one for flush write. Changes since v1: - Merge the gpio-aspeed-g7.c into the gpio-aspeed.c. - Create the llops in gpio-aspeed.c for flexibility. Billy Tsai (6): dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 gpio: aspeed: Remove the name for bank array gpio: aspeed: Create llops to handle hardware access gpio: aspeed: Support G7 Aspeed gpio controller gpio: aspeed: Change the macro to support deferred probe gpio: aspeed: Add the flush write to ensure the write complete. .../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +- drivers/gpio/gpio-aspeed.c | 589 +++++++++++------- 2 files changed, 381 insertions(+), 227 deletions(-)