From patchwork Tue Sep 24 09:50:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13810638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4058CCF9C6B for ; Tue, 24 Sep 2024 09:57:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To: Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=6NebSt8Wdrgk6Di3RsSEE+fY6ux4r4XoR+rlakITjhA=; b=e3E4Ee1lowH92P jh9XEux/1/6MrkZ2dlJwoDIuCjJjChCtKocjmXCvUCaJjiMgj5iJo50AvvbX1p9By9QXc7UPhiYJc UvuEZbWgwOb7VRotnVomElW300lOjeG/JfnZ/3vUcehgklFXTOKZEQSIwtYoeYVPsMReCYJ6oVADh uxSstSwX0oWzmjIL6upLEjkoUiunxk9QmFb15YK+7wh7gaOXGGU5RH+7g4YF9F82H+4Yer1JVfXtM RrzDmta1TP+hrHvdHQodpnqOX2F6GGG7FmEYIzS+m6eYDnIIPRShT7xztO8i1VKMoXedIKpkp+/9M cVwqQ4z66hNaZOkECTxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1st2IE-00000001u39-0Ne5; Tue, 24 Sep 2024 09:57:14 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1st2CY-00000001svo-3rAa for linux-arm-kernel@lists.infradead.org; Tue, 24 Sep 2024 09:51:25 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48O9p4g2003146; Tue, 24 Sep 2024 04:51:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727171464; bh=6NebSt8Wdrgk6Di3RsSEE+fY6ux4r4XoR+rlakITjhA=; h=From:Subject:Date:To:CC; b=oEvMqQbTs3spbyUKIhExPLCvbp4LFHe9vnCsiA7OR1wndHjAOwRg3xAz1eBIVScQC bIHrCe7PAzdFf9IRL4hLRl5scBnX2jaanB69MjqEUzAhK9+xEi6I89QX9WnORBFyqH G+1p+kcex9dFJqDVC2bynJnEBh65sQ8xR4YJyTgc= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48O9p32F000749 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 24 Sep 2024 04:51:03 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 24 Sep 2024 04:51:02 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 24 Sep 2024 04:51:02 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48O9owSp017217; Tue, 24 Sep 2024 04:50:59 -0500 From: Dhruva Gole Subject: [PATCH v5 0/6] ti: k3-am62{a,p}x-sk: add opp frequencies Date: Tue, 24 Sep 2024 15:20:40 +0530 Message-ID: <20240924-ti-cpufreq-fixes-v5-v5-0-cbe16b9ddb1b@ti.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAHCL8mYC/03MQQ6CMBCF4auQWTukrRRbV97DuIB2CpMIxRaJC eHuNq5cfnn53w6ZElOGa7VDoo0zx7lAnypwYzcPhOyLQQnVCKsaXBnd8g6JXhj4Qxk3jb7vz6S FbvvWQSmXRL+thPdHcUhxwnVM1P19SSuMMsLW8tJoY1GixyE+6bZy7eIEx/EFiXtPrp0AAAA= X-Change-ID: 20240924-ti-cpufreq-fixes-v5-dbb3e5056b6c To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727171458; l=5099; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=wsy4VuWlWCWiwuLeUvDVMNXTk4Izkw42hm7B9/z6TAo=; b=V0JVGEhrNtFHg5lCiG8sRPmhROBUrER+xn+dqv904c2lZj1y5BltoEOwxUD/ruXdtfaG7R5F0 SbbixlKGPELCyeTbkHq0JmIVsLqv1hWhFzejRFWCcKBIXq3f2H/bQRi X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240924_025123_184754_5208137C X-CRM114-Status: GOOD ( 22.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello everyone This series adds in the OPPs for the Cortex-A53s on the AM62Ax and AM62Px SoC families along with the defining the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID which we can use to properly limit the OPPs available for that variant. Moreover, it also adds a driver cleanup where we can finally get rid of the rev_offsets and zero the efuse_offsets as they are now taken from socinfo and DT efuse node register respectively. This series has been tested on all devices that it affects and has been confirmed to cause no known regressions. Test logs: https://gist.github.com/DhruvaG2000/63f5e28636d52787488f776e5bf39498 **NOTE:** Special attention needed on the driver patch 5/6 & 6/6: Viresh and Vignesh, The driver fix needs to go with PATCH 5/6. Subject: [PATCH V4 5/6] arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon That patch fixes the efuse offset in the AM625 DT. Without it, the driver will read from an incorrect efuse offset, and end up breaking things in -next till all the DT changes make it in. Hence, it would be preferrable if this entire series goes via a single maintainer's tree. Viresh, perhaps if you can ack this single patch, then Vignesh could take it up if there are no objections? I am sorry that this breaks compatibility with older AM625 devicetree. However, the old devicetree was marking the entire wkup_conf as "syscon", "simple-mfd" which was wrong and needed to be fixed. This series finally tries to bring order to DT and the driver. However, if there is still any way to maintain the backward compatibility, then I am open to suggestions. Please try and understand here that the ask for backward compatibility here is to ask the driver to support a case where the register offset itself was to be picked from a different node. I am not sure if there's any cleaner way to do this. Changelog: --- Changes in v5: - Based on Andrew's review on v4 of "arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon", - s/syscon@43000000/bus@43000000/ - Drop the "reg = <>;" line - Link to v4: https://lore.kernel.org/all/20240919082809.174589-1-d-gole@ti.com/ Changes in v4: - Add 2 more patches to this series: - Driver cleanup as described above. - AM625 DT fixups (Link to v1 of that patch: https://lore.kernel.org/all/20240902093222.2828345-2-d-gole@ti.com/) - Link to v3: https://lore.kernel.org/all/20240826-opp-v3-0-0934f8309e13@ti.com/ Changes in v3: - Miscellaneous spelling fixes in commit body - Link to v2: https://lore.kernel.org/r/20240823-opp-v2-0-e2f67b37c299@ti.com Changes in v2: - Expanded on commit descriptions - Split board file and SoC fdt changes into different patches - Link to v1: https://lore.kernel.org/r/20240809-opp-v1-0-fea8efeaf963@ti.com --- Bryan Brattlof (4): arm64: dts: ti: k3-am62a: add opp frequencies arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry arm64: dts: ti: k3-am62p: add opp frequencies arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Dhruva Gole (2): arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon cpufreq: ti-cpufreq: Update efuse/rev offsets in AM62 family arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 7 ++- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 ++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 ++++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++ .../dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 ++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 ++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 +++++++++++++++++ drivers/cpufreq/ti-cpufreq.c | 5 +- 9 files changed, 134 insertions(+), 6 deletions(-) base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 -- 2.34.1 --- Bryan Brattlof (4): arm64: dts: ti: k3-am62a: add opp frequencies arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry arm64: dts: ti: k3-am62p: add opp frequencies arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Dhruva Gole (2): arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon cpufreq: ti-cpufreq: Update efuse/rev offsets in AM62 family arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 +++-- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 ++++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 ++++++++++++++++++++++ .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 ++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++++ drivers/cpufreq/ti-cpufreq.c | 5 +-- 9 files changed, 135 insertions(+), 8 deletions(-) --- base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 change-id: 20240924-ti-cpufreq-fixes-v5-dbb3e5056b6c Best regards,