[0/2] arm64: errata: Expand speculative SSBS workaround once more

Message

Mark Rutland Sept. 30, 2024, 11:17 a.m. UTC

In a recent bunch of SDEN updates, it was revealed that Cortex-A715 and
Neoverse-N3 suffer from the common SSBS erratum whereby an MSR to the
SSBS special-purpose register does not affect subsequent speculative
instructions, permitting speculative store bypassing for a window of
time.

These patches enable the mitigation for Cortex-A715 and Neoverse-N3.

Fingers crossed, this should be the last batch of CPUs affected by this
erratum.

I haven't given this a Cc stable since (as with the prior batches) some
manual work is necessary to backport to some of the stable trees, and
it'll be easier to prepare all the backports manually in one go.

Mark.

Mark Rutland (2):
  arm64: cputype: Add Neoverse-N3 definitions
  arm64: errata: Expand speculative SSBS workaround once more

 Documentation/arch/arm64/silicon-errata.rst | 4 ++++
 arch/arm64/Kconfig                          | 2 ++
 arch/arm64/include/asm/cputype.h            | 2 ++
 arch/arm64/kernel/cpu_errata.c              | 2 ++
 4 files changed, 10 insertions(+)

Comments

Catalin Marinas Oct. 1, 2024, 1:02 p.m. UTC | #1

On Mon, 30 Sep 2024 12:17:03 +0100, Mark Rutland wrote:
> In a recent bunch of SDEN updates, it was revealed that Cortex-A715 and
> Neoverse-N3 suffer from the common SSBS erratum whereby an MSR to the
> SSBS special-purpose register does not affect subsequent speculative
> instructions, permitting speculative store bypassing for a window of
> time.
> 
> These patches enable the mitigation for Cortex-A715 and Neoverse-N3.
> 
> [...]

Applied to arm64 (for-next/fixes), thanks!

[1/2] arm64: cputype: Add Neoverse-N3 definitions
      https://git.kernel.org/arm64/c/924725707d80
[2/2] arm64: errata: Expand speculative SSBS workaround once more
      https://git.kernel.org/arm64/c/081eb7932c2b