[00/47] KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers

Message

Anshuman Khandual Oct. 1, 2024, 2:43 a.m. UTC

This series enables fine grained undefined for FEAT_FGT2 managed registers
via adding their respective FGT and CGT trap configuration. But first this
adds many system register definitions in tools/sysreg, which are required
there after.

patches 1-44: define system registers in tools/sysreg format
patch     45: enables FEAT_FGT2 registers access from virtual EL2
patch     46: enables FGT for FEAT_FGT2
patch     47: enables CGT for FEAT_FGT2

Some notes:

As kvm_has_feat() does not support non-ID registers following replacements
have been made for validating presence of correspnding features

- ID_AA64DFR0_EL1.ExtTrcBuff is tested for HDFGRTR2_EL2.nPMSDSFR_EL1
- ID_AA64DFR0_EL1.PMSVer is tested for HDFGRTR2_EL2.nPMSDSFR_EL1

Following FGT enabled registers don't have corresponding CGT requirements

- TRCITECR_EL1
- PMSSCR_EL1
- PMCCNTSVR_EL1
- PMICNTSVR_EL1
- RCWSMASK_EL1
- ERXGSR_EL1
- PFAR_EL1

Changes in V2:

- Added all system register definitions required for FEAT_FGT2 traps
- Added all system register access traps managed with new FEAT_FGT2
  i.e HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_GROUP, HFGWTR2_GROUP and
  HFGITR2_GROUP for their VNCR access, FGT and CGT
- Added all FGT for all register accesses managed with FEAT_FGT2
- Added all CGT for all register accesses managed with FEAT_FGT2

Changes in RFC V1:

https://lore.kernel.org/linux-arm-kernel/[e-mail]/

Cc: Marc Zyngier <[e-mail]>
Cc: Oliver Upton <[e-mail]>
Cc: James Morse <[e-mail]>
Cc: Suzuki K Poulose <[e-mail]>
Cc: Catalin Marinas <[e-mail]>
Cc: Will Deacon <[e-mail]>
Cc: Mark Brown <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]

Anshuman Khandual (47):
  arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
  arm64/sysreg: Update register fields for ID_AA64DFR0_EL1
  arm64/sysreg: Update register fields for ID_AA64PFR0_EL1
  arm64/sysreg: Add register fields for ID_AA64DFR2_EL1
  arm64/sysreg: Add register fields for HDFGRTR2_EL2
  arm64/sysreg: Add register fields for HDFGWTR2_EL2
  arm64/sysreg: Add register fields for HFGITR2_EL2
  arm64/sysreg: Add register fields for HFGRTR2_EL2
  arm64/sysreg: Add register fields for HFGWTR2_EL2
  arm64/sysreg: Add register fields for MDSELR_EL1
  arm64/sysreg: Add register fields for PMSIDR_EL1
  arm64/sysreg: Add register fields for TRBIDR_EL1
  arm64/sysreg: Add register fields for TRBMPAM_EL1
  arm64/sysreg: Add register fields for PMSDSFR_EL1
  arm64/sysreg: Add register fields for SPMDEVAFF_EL1
  arm64/sysreg: Add register fields for PFAR_EL1
  arm64/sysreg: Add register fields for PMIAR_EL1
  arm64/sysreg: Add register fields for PMECR_EL1
  arm64/sysreg: Add register fields for PMUACR_EL1
  arm64/sysreg: Add register fields for PMCCNTSVR_EL1
  arm64/sysreg: Add register fields for SPMSCR_EL1
  arm64/sysreg: Add register fields for SPMACCESSR_EL1
  arm64/sysreg: Add register fields for PMICNTR_EL0
  arm64/sysreg: Add register fields for PMICFILTR_EL0
  arm64/sysreg: Add register fields for SPMCR_EL0
  arm64/sysreg: Add register fields for SPMOVSCLR_EL0
  arm64/sysreg: Add register fields for SPMOVSSET_EL0
  arm64/sysreg: Add register fields for SPMINTENCLR_EL1
  arm64/sysreg: Add register fields for SPMINTENSET_EL1
  arm64/sysreg: Add register fields for SPMCNTENCLR_EL0
  arm64/sysreg: Add register fields for SPMCNTENSET_EL0
  arm64/sysreg: Add register fields for SPMSELR_EL0
  arm64/sysreg: Add register fields for PMICNTSVR_EL1
  arm64/sysreg: Add register fields for SPMIIDR_EL1
  arm64/sysreg: Add register fields for SPMDEVARCH_EL1
  arm64/sysreg: Add register fields for SPMCFGR_EL1
  arm64/sysreg: Add register fields for PMSSCR_EL1
  arm64/sysreg: Add register fields for PMZR_EL0
  arm64/sysreg: Add register fields for SPMCGCR0_EL1
  arm64/sysreg: Add register fields for SPMCGCR1_EL1
  arm64/sysreg: Add register fields for MDSTEPOP_EL1
  arm64/sysreg: Add register fields for ERXGSR_EL1
  arm64/sysreg: Add register fields for SPMACCESSR_EL2
  arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2
  KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2
  KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling
  KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers

 arch/arm64/include/asm/kvm_arm.h        |  22 +
 arch/arm64/include/asm/kvm_host.h       |  12 +
 arch/arm64/include/asm/sysreg.h         |   6 +
 arch/arm64/include/asm/vncr_mapping.h   |   5 +
 arch/arm64/kvm/emulate-nested.c         | 444 +++++++++++
 arch/arm64/kvm/hyp/include/hyp/switch.h |  26 +
 arch/arm64/kvm/nested.c                 |  52 ++
 arch/arm64/kvm/sys_regs.c               |  64 ++
 arch/arm64/tools/sysreg                 | 938 +++++++++++++++++++++++-
 9 files changed, 1564 insertions(+), 5 deletions(-)

Comments

Mark Brown Oct. 2, 2024, 3:52 p.m. UTC | #1

On Tue, Oct 01, 2024 at 08:13:09AM +0530, Anshuman Khandual wrote:
> This series enables fine grained undefined for FEAT_FGT2 managed registers
> via adding their respective FGT and CGT trap configuration. But first this
> adds many system register definitions in tools/sysreg, which are required
> there after.

One top level comment: these are updates for DDI0601 2024-06 but we've
now got 2024-09 available.

Anshuman Khandual Oct. 3, 2024, 3:54 a.m. UTC | #2

On 10/2/24 21:22, Mark Brown wrote:
> On Tue, Oct 01, 2024 at 08:13:09AM +0530, Anshuman Khandual wrote:
>> This series enables fine grained undefined for FEAT_FGT2 managed registers
>> via adding their respective FGT and CGT trap configuration. But first this
>> adds many system register definitions in tools/sysreg, which are required
>> there after.
> 
> One top level comment: these are updates for DDI0601 2024-06 but we've
> now got 2024-09 available.

Right, guess this new release i.e 2024-09 just happened recently because
IIRC version 2024-06 was marked as the latest until last weekend. I will
revisit all the above register definitions for 2024-09 release update and
will also update their commit messages as required.