From patchwork Tue Oct 8 08:14:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 13825955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEC1FCED276 for ; Tue, 8 Oct 2024 08:17:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=gAC2jvnrzh4Pu0XmhNLuUpc8pqd31rD8Wau0w6O/Nzs=; b=S115cV+jRNZFXH UxEGT+oygxiffQzA03Bah6jaBZ+dXH+fL8LzUt7EEn/sa5v2Ehigoc7jcdfPXsD9Tef1A168n3Gwc yX+7uT50lN3CMbVksRsOJkY1NmsmO7BMa+y2PpztX/4HBUEH6GUZGx35RDXgMy30a5ZgyjykGcocT Bbm+QIsNWbVnR9n/hHtYq+KWGN5fWHIobPDo9LsAWonM1pzl1I/x59QQeLmPONhC23ExgXkQZw9b4 9prI+yKmFc78JgCSqJ2TenUSztWD167v8GPXKS/L9zqNfLdlb2JN2Zz7YDEnSSsaVmAtPtQ2jDbvA Fo/Q+r5Cj8rglQy7nT+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sy5PX-00000004z9q-1eS6; Tue, 08 Oct 2024 08:17:39 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sy5Mx-00000004yHp-2Hop for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2024 08:15:01 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 8 Oct 2024 16:14:50 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 8 Oct 2024 16:14:50 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v7 0/7] Add Aspeed G7 gpio support Date: Tue, 8 Oct 2024 16:14:43 +0800 Message-ID: <20241008081450.1490955-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241008_011459_606993_E2E9C4F4 X-CRM114-Status: GOOD ( 14.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Aspeed 7th generation SoC features two GPIO controllers: one with 12 GPIO pins and another with 216 GPIO pins. The main difference from the previous generation is that the control logic has been updated to support per-pin control, allowing each pin to have its own 32-bit register for configuring value, direction, interrupt type, and more. This patch serial also add low-level operations (llops) to abstract the register access for GPIO registers and the coprocessor request/release in gpio-aspeed.c making it easier to extend the driver to support different hardware register layouts. Change since v6: - Reorder the patch. - Reoder the llops assignments in the same order as the member declarations. - Add a comment explaining the logic used for the debounce timer array. Change since v5: - Reorder the aspeed_gpio_llops api - Add aspeed_gpio prefix for all of the api - Add mask value check before field_get and field_prep - Separate the devm_clk_get_enabled modification into a new patch. Change since v4: - Add `reg_bank_get` callback - `reg_bits_get` -> `reg_bit_get - `dcache_require` -> `require_dcache` - Use `devm_clk_get_enabled` to get the clock source - g4 specific api doesn't need to use the callback function Change since v3: - Add `privilege_ctrl` and `privilege_init` callback - Use `bool aspeed_gpio_support_copro()` api to replace the `cmd_source_supoort` flag - Add the `dcache_require` flag and move the dcache usage into the reg_bit_set callback - `reg_bits_set` -> `reg_bit_set` and `reg_bits_read` -> `reg_bits_get` - `bool copro = 0` -> `bool copro = false` - `if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bits_get) return -EINVAL;` - Correct the access of reg_irq_status - Remove __init attribute to fix the compiler warning Change since v2: - Correct minItems for gpio-line names - Remove the example for ast2700, because it's the same as the AST2600 - Fix the sparse warning which is reported by the test robot - Remove the version and use the match data to replace it. - Add another two patches one for deferred probe one for flush write. Changes since v1: - Merge the gpio-aspeed-g7.c into the gpio-aspeed.c. - Create the llops in gpio-aspeed.c for flexibility. Billy Tsai (7): gpio: aspeed: Add the flush write to ensure the write complete. gpio: aspeed: Use devm_clk api to manage clock source gpio: aspeed: Change the macro to support deferred probe gpio: aspeed: Remove the name for bank array gpio: aspeed: Create llops to handle hardware access dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 gpio: aspeed: Support G7 Aspeed gpio controller .../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +- drivers/gpio/gpio-aspeed.c | 620 +++++++++++------- 2 files changed, 408 insertions(+), 231 deletions(-)