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Wed, 30 Oct 2024 03:18:26 -0700 (PDT) Date: Wed, 30 Oct 2024 11:18:04 +0100 Mime-Version: 1.0 X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-Developer-Signature: v=1; a=openpgp-sha256; l=2684; i=ardb@kernel.org; h=from:subject; bh=nOLFU4fVeqjBBVbYqOn8j3eNn//s20k3b7v6vSDc/tE=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIV2J/c7HrMULbjVuyex5a9d5ZUr4lSvt+iHzp0+cMWeP8 Ja1sakCHaUsDGIcDLJiiiwCs/++23l6olSt8yxZmDmsTCBDGLg4BWAi/+cw/LPs268tdWH/guai PT6aD5hNrvE/EdHRPiJ7appPyjJT3zuMDH8MJxotVSoPZu6fd76/vWDlnQq5XJ6HH1o+Xto7YVH AEgYA X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog Message-ID: <20241030101803.2037606-10-ardb+git@google.com> Subject: [RFC PATCH 0/8] arm64: Simplify VA space configurations From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel , Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland , Ryan Roberts , Anshuman Khandual , Kees Cook X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241030_031828_779990_0FB68D07 X-CRM114-Status: GOOD ( 13.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ard Biesheuvel For historical reasons, we currently support many combinations of page size and virtual address space size: - the original arm64 port used only 3 levels of paging (4k/39 bits), and the 4 level configuration was only added later - LVA support on 64k pages could not be disabled at boot, and so it was added as a completely separate configuration, even though the number of translation levels is the same - 16k pages gains only 1 bit of VA space when going from 3 to 4 levels of translation, and so both are supported - 16k/36 bits is supported under CONFIG_EXPERT, but 36 bits is a bit on the small side for the kernel. Let's simplify this, by - removing the configurations that are also the fallbacks on LPA/LPA2 capable hardware, - converting 36, 42 and 39 bit configurations into reduced definitions of TASK_SIZE, while keeping the larger VA space on the kernel side, - dropping 16k/48 bits altogether. The remaining configurations always support up to 52-bit virtual addressing on the kernel side, and implement the reduced userland VA space sizes by skipping levels when programming TTBR0_EL1. This is a quick and dirty hack, but sufficient for the purposes of this RFC. Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Rutland Cc: Ryan Roberts Cc: Anshuman Khandual Cc: Kees Cook Ard Biesheuvel (8): arm64/Kconfig: force ARM64_PAN=y when enabling TTBR0 sw PAN arm64/Kconfig: fix ARCH_MMAP_RND_BITS_MAX for 52-bit virtual addressing arm64/Kconfig: eliminate 64k/48-bit VA combination arm64/Kconfig: eliminate 4k/48-bit VA combination arm64/Kconfig: Drop support for 47-bit virtual addressing arm64/Kconfig: Drop support for 48-bit virtual addressing arm64/mm: Use reduced VA sizes (36/39/42 bits) only for user space arm64/mm: Account for reduced VA sizes in T0SZ and skip the levels arch/arm64/Kconfig | 89 ++++++++------------ arch/arm64/include/asm/assembler.h | 2 +- arch/arm64/include/asm/memory.h | 4 - arch/arm64/include/asm/mmu_context.h | 9 +- arch/arm64/include/asm/pgtable-hwdef.h | 2 - arch/arm64/include/asm/processor.h | 6 +- arch/arm64/kernel/cpufeature.c | 2 - arch/arm64/kernel/head.S | 4 - arch/arm64/mm/init.c | 4 +- arch/arm64/mm/pgd.c | 9 +- arch/arm64/mm/proc.S | 2 - 11 files changed, 52 insertions(+), 81 deletions(-)