[0/2] clk: amlogic: Limit the rate boundaries of clk_hw

Message

Chuan Liu via B4 Relay Jan. 10, 2025, 11:47 a.m. UTC

The following figure shows a rough hardware connection block diagram
between "clk_hw" and "clk_consumer". The frequency of the clock is
affected by the following two situations:
1. The hardware limitations of "clk_hw" itself. For instance, the
effective output frequency range of some PLL designs is 3G to 6G.
2. The timing constraints for the electrical "line" between "clk_hw" and
"clk_consumer". Timing constraints are applied to each clock network
within the chip, which limits the maximum frequency of the "line".

   ________             ________________
  |        |   line    |                |
  | clk_hw |-----+---->| clk_consumer 1 |
  |________|     |     |________________|
                 |
		 |            ...
                 |      ________________
		 |     |                |
		 +---->| clk_consumer n |
		       |________________|

The frequency boundaries specified for clk_hw in the patch are the
combined frequency boundaries of "clk_hw" and "line", just like the
frequency boundaries obtained after clk_core_get_boundaries() combines
each clks_node.

The min_rate/max_rate of the clk_hw can be described in a less strict
way as follows:
* min_rate = max("clk_hw", "line");
* max_rate = min("clk_hw", "line");

Signed-off-by: Chuan Liu <[e-mail]>
---
Chuan Liu (2):
      clk: Add initialize the rate boundaries of the clk provider
      clk: amlogic: c3: Limit the rate boundaries of clk_hw

 drivers/clk/clk.c                  |  4 ++--
 drivers/clk/meson/c3-peripherals.c | 21 +++++++++++++++++++++
 drivers/clk/meson/c3-pll.c         |  4 ++++
 include/linux/clk-provider.h       |  4 ++++
 4 files changed, 31 insertions(+), 2 deletions(-)
---
base-commit: 1e1fd26ed4ca05cc1f0e5857918da4dd54967f7d
change-id: 20250110-limit-rate-range-of-clk-61626c7b6dc5

Best regards,