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([78.9.4.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384ce0529sm740943866b.43.2025.01.21.04.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 04:56:14 -0800 (PST) From: Lukasz Czechowski To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quentin.schulz@cherry.de, Lukasz Czechowski Subject: [PATCH v2 0/2] Disable DMA on secondary UART on PX30 Ringneck Date: Tue, 21 Jan 2025 13:56:02 +0100 Message-ID: <20250121125604.3115235-1-lukasz.czechowski@thaumatec.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250121_045618_042516_B728B7B2 X-CRM114-Status: GOOD ( 11.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PX30-uQ7 (Ringneck) SoM has two external UARTs, connected to uart0 and uart5 controllers on the PX30 SoC. The uart5 does not expose RTS/CTS pins on the Q7 connector, as they are used for different purposes. It was observed that UART controllers without hardware flow controller behave unstable if the DMA is enabled. This patch series moves the pinctrl-0 to SoM dtsi file and uses /delete-property/ to remove DMA from this UART controller. ---- Changes v2: - Update commit message of patch 1/2 - Add Cc: stable@vger.kernel.org Lukasz Czechowski (2): arm64: dts: rockchip: Move uart5 pin configuration to SoM dtsi arm64: dts: rockchip: Disable DMA for uart5 on px30-ringneck arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 - arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-)