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Fri, 28 Aug 2020 06:53:22 -0700 (PDT) From: Cristian Ciocaltea To: =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Rob Herring , Peter Korsgaard Subject: [PATCH v2 0/4] Add initial support for RoseapplePi SBC Date: Fri, 28 Aug 2020 16:53:16 +0300 Message-Id: X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200828_095326_227339_E00534C6 X-CRM114-Status: GOOD ( 13.95 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patchset enables basic support for RoseapplePi, relying exclusively on the existing infrastructure for the Actions Semi Owl SoCs (thanks to Andreas and Mani for making this possible). The SBC is powered by the Actions Semi S500 SoC and comes with 2GB RAM, uSD slot and optional eMMC storage. For more details, please check: http://roseapplepi.org/index.php/spec/ The upcoming patches will improve this initial support by adding the missing bits and pieces to the S500 clock management unit, which is a prerequisite for providing an S500 pinctrl and gpio driver, in order to eventually enable access to additional functionality like I2C and MMC. Thanks and regards, Cristian Ciocaltea Changes in v2: - Added Reviewed-by and Acked-by tags from Rob - Added Reviewed-by tags from Peter - Rebased series onto v5.9-rc2 Cristian Ciocaltea (4): arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers dt-bindings: Add vendor prefix for RoseapplePi.org dt-bindings: arm: actions: Document RoseapplePi arm: dts: owl-s500: Add RoseapplePi .../devicetree/bindings/arm/actions.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 +++++++++++++++++++ arch/arm/boot/dts/owl-s500.dtsi | 6 +-- 5 files changed, 54 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts