From patchwork Tue Sep 8 08:20:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11762973 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 565701599 for ; Tue, 8 Sep 2020 08:21:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25DB121D81 for ; Tue, 8 Sep 2020 08:21:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lYi1kCx+"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aVUgIyhA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 25DB121D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=J6ZUsgG+0KgjK+wo2nvtmsPJkuR8uDdg7tXcpRFZQcM=; b=lYi1kCx+NL3NiGwHy517jBB1HF wfk/uu/T4KMrHcA4yBzrwOgKRyg2M07zMy2bM6GF9Np7v4GOysSL2buxcA/w343NKXYLLD49a88XT TILk8+RgkDvJT+RZ4vDoXtDnJAWBLYJ9VIZ8me28cLZnCu3pvH8pe8xlyS9ymI0FLQ6CBdar2EhMX vqlXEbgIssvd2C+j9JVkQVtqyT4pmwooxVh00oHoCQqEr665a5aWDgF2I3AIS+jNOtPc6H140Wzvu NMuC0cPIYEyelMXBerXmSIpMxEGNk/TUDvZ1pYPUS889uG4sb21+IFp2PEQ5Kt/PEHhIQJfRIUWPS 4C/56oOQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFYsE-0004c7-GT; Tue, 08 Sep 2020 08:21:06 +0000 Received: from mail-ed1-x541.google.com ([2a00:1450:4864:20::541]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFYs4-0004Wz-2U; Tue, 08 Sep 2020 08:21:02 +0000 Received: by mail-ed1-x541.google.com with SMTP id n13so15078548edo.10; Tue, 08 Sep 2020 01:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=63STSyHRLazmb7nSKR8rGI5k4M8WJtXmYGJdf9TDYBs=; b=aVUgIyhAUnxSTk/UkOHy70pKspSNsP/kxLtvkI+yxJaokuR5x8I+MaN9uUZFSp0y2a 7P3rtQI1cTRnJ5X/u/Y81bLWpBFEr2EK9pttyGdLgsORjwv3RfirJb/Cop7jjHpQsY1v LgFKUVqy2K0gKEY9hgW4SYLeKmebb6F1/XUozoPvXZEN+BtdDadcPTqAhqV0Fn/Ca3wk TYUFsqRmRkGpgGaWOqHDkVmNHc9srWqRUvSFv2o7uhn0WmuSLvniwH8kg4bFDpk6C0Wt d+tFB/nURlYwOFMEIYYrdw9i+sAnP54LQ5TtyHcZ6ZLQD/2MetkzY3FAvXwgVm2zeAW/ s6hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=63STSyHRLazmb7nSKR8rGI5k4M8WJtXmYGJdf9TDYBs=; b=rXZL0YyRRcKsXo4f4hWBPwWJesVAm9K6oIn5pCJzaKtE9Anlx7Hg0Wp30/UWeqHHfI S23aIiT/sfcDGA12NtAGWN0P+xgPtU9AK9Rww2Ck32CcWLduDk+iBg5qrkEb3VnWYrPT SL3zVXTztXvYexyydQhBC1f3JSXhv0ws2XKw3744p32M8D/ZuhJOTua4V0KnrghEoDFP GGZ92p2MBtBonUvQQfSxDtrioHI9szirsB4Qu2Jt/Qj0C1UBHB6LFQYkDgGrOgM4yOur tLoZPIs5/TfI7qeTewofv1pLszVyJAcrvHprnhaRiHaY9mlCzUIbcSF7HTwd5foz+Kc6 IP4w== X-Gm-Message-State: AOAM530D8XPUxKhDXH4e1IM9n9u8Nlkbj8mBzXVaKgvFr3OME7U5TlEa oB7B54iFhna4GLmppZ+9w4Y= X-Google-Smtp-Source: ABdhPJw1KTXm9rLt7JG8xTpbt4XCQYBwwTuJs1QMGPu103vrbGICvY6QbNyT8rr3CfqsY+Z57kS59Q== X-Received: by 2002:aa7:c693:: with SMTP id n19mr26634894edq.101.1599553253064; Tue, 08 Sep 2020 01:20:53 -0700 (PDT) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id g24sm13172326edy.51.2020.09.08.01.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 01:20:52 -0700 (PDT) From: Cristian Ciocaltea To: Marc Zyngier , Rob Herring , Manivannan Sadhasivam , Thomas Gleixner , Jason Cooper , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH v6 0/3] Add Actions Semi Owl family sirq support Date: Tue, 8 Sep 2020 11:20:47 +0300 Message-Id: X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_042056_199411_480309BD X-CRM114-Status: GOOD ( 22.46 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:541 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, parthiban@linumiz.com, Saravanan Sekar , linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch series adds support for the external interrupt controller (SIRQ) found in the Actions Semi Owl family of SoC's (S500, S700 and S900). The controller handles up to 3 external interrupt lines through dedicated SIRQ pins. This is a rework of the patch series submitted some time ago by Parthiban Nallathambi: https://lore.kernel.org/lkml/20181126100356.2840578-1-pn@denx.de/ Please note I have dropped, for the moment, the S700 related patches since I do not own a compatible hardware for testing. I'm using instead an S500 SoC based board for which I have already provided the initial support: https://lore.kernel.org/lkml/cover.1598621459.git.cristian.ciocaltea@gmail.com/ Additionally, I have taken the authorship for the driver patch, considering the original code has been already modified to a great extent and I'm firmly committed to maintaining it in the long run. The SIRQ controller support is a prerequisite of the upcoming MFD driver for the Actions Semi ATC260x PMICs. Thanks and regards, Cristi Changes in v6: - Integrated binding doc related feedback from Rob and Marc - Updated cover letter to handle the authorship issue indicated by Mani - Rebased patch series on v5.9-rc4 Changes in v5: - Integrated Marc's review (more details in the driver patch changelog) - Rebased patch series on v5.9-rc1 Changes in v4: - Simplified the DTS structure: * dropped 'actions,sirq-shared-reg' node, now the differentiation between SoC variants is handled via the compatible property * dropped 'actions,sirq-reg-offset', now controller base address in DTS points to SIRQ0 register, so no additional information is required for S500 and S700, while for S900 SoC the offsets of SIRQ1 and SIRQ2 regs are provided by the driver * 'actions,ext-irq-range' was replaced with 'actions,ext-interrupts', an array of the GIC interrupts triggered by the controller - Fixed wrong INTC_EXTCTL_TYPE_MASK definition - Removed redundant irq_fwspec checks in owl_sirq_domain_alloc() - Improved error handling in owl_sirq_of_init() - Added yaml binding document - Dropped S700 related DTS patches for lack of testing hardware: * arm64: dts: actions: Add sirq node for Actions Semi S700 * arm64: dts: actions: s700-cubieboard7: Enable SIRQ - Updated MAINTAINERS - Rebased patchset on kernel v5.8 - Cosmetic changes * Ordered include statements alphabetically * Added comment to owl_sirq_set_type() describing conversion of falling edge or active low signals * Replaced IRQF_TRIGGER_* with corresponding IRQ_TYPE_* variants * Ensured data types and function naming are consistent regarding the 'owl_sirq' prefix Changes in v3 (Parthiban Nallathambi): - Set default operating frequency to 24MHz - Falling edge and Low Level interrupts translated to rising edge and high level - Introduced common function with lock handling for register read and write - Used direct GIC interrupt number for interrupt local hwirq and finding offset using DT entry (range) when registers are shared - Changed irq_ack to irq_eoi - Added translation method for irq_domain_ops - Clearing interrupt pending based on bitmask for edge triggered - Added pinctrl definition for sirq for cubieboard7. This depends on, https://lore.kernel.org/patchwork/patch/1012859/ Changes in v2 (Parthiban Nallathambi): - Added SIRQ as hierarchical chip GIC <----> SIRQ <----> External interrupt controller/Child devices - Device binding updates with vendor prefix - Register sharing handled globally and common init sequence/data for all actions SoC family Cristian Ciocaltea (3): dt-bindings: interrupt-controller: Add Actions SIRQ controller binding irqchip: Add Actions Semi Owl SIRQ controller MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller .../actions,owl-sirq.yaml | 65 ++++ MAINTAINERS | 2 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-owl-sirq.c | 359 ++++++++++++++++++ 4 files changed, 427 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml create mode 100644 drivers/irqchip/irq-owl-sirq.c