From patchwork Wed Nov 18 10:30:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 11914737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E93C63697 for ; Wed, 18 Nov 2020 10:32:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 809C822266 for ; Wed, 18 Nov 2020 10:32:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CemfvHzx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 809C822266 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=nORQB3Gcqd/iyxHnQiKEwujrOLbuPNLgIPJhav21RS8=; b=CemfvHzxSfZ5zFj9MtFg9JTs3Y DFRwSawfwdd2c1R5LumbE4WcNeyvl0DGjIFg8O8LUm3YN8iIxOMuX3/T89bd5LdcYBcSElB5oZxyK 2oDpn4nzA4j48zPCYSzUJLmfUXVKb/mcwJXEJracSjnQLGs414IrkzvbHtb49YqH+DFdNLi90rGRI YCgouSvlq8JRgVTUy5Ze/LU4GkSG/61eJaDlFvLRZ7c+7aKPBDzFjSY6I+WbM5XVVeqaTAZOI63sX AqQeO3e6wjPOwSrqm6FeewOMmYEQ+WR7YD4DiZN3OSra4Pn/vekkGiee2EdSX4vBT+K+mfTxCZ8Ly OYI4nLLA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfKkL-0002Nv-9M; Wed, 18 Nov 2020 10:31:29 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfKkC-0002KH-Jw for linux-arm-kernel@lists.infradead.org; Wed, 18 Nov 2020 10:31:21 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 54FCC4406E6; Wed, 18 Nov 2020 12:30:57 +0200 (IST) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Linus Walleij , Bartosz Golaszewski Subject: [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support Date: Wed, 18 Nov 2020 12:30:41 +0200 Message-Id: X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201118_053120_916770_D2E3FD41 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Baruch Siach , Jason Cooper , linux-pwm@vger.kernel.org, Gregory Clement , linux-gpio@vger.kernel.org, Chris Packham , Thomas Petazzoni , Ralph Sennhauser , Sascha Hauer , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The gpio-mvebu driver supports the PWM functionality of the GPIO block for earlier Armada variants like XP, 370 and 38x. This series extends support to newer Armada variants that use CP11x and AP80x, like Armada 8K and 7K. This series adds adds the 'pwm-offset' property to DT binding. 'pwm-offset' points to the base of A/B counter registers that determine the PWM period and duty cycle. The existing PWM DT binding reflects an arbitrary decision to allocate the A counter to the first GPIO block, and B counter to the other one. In attempt to provide better future flexibility, the new 'pwm-offset' property always points to the base address of both A/B counters. The driver code still allocates the counters in the same way, but this might change in the future with no change to the DT. Tested AP806 and CP110 (both) on Armada 8040 based system. Baruch Siach (5): gpio: mvebu: update Armada XP per-CPU comment gpio: mvebu: switch pwm duration registers to regmap gpio: mvebu: add pwm support for Armada 8K/7K arm64: dts: armada: add pwm offsets for ap/cp gpios dt-bindings: ap806: document gpio pwm-offset property .../arm/marvell/ap80x-system-controller.txt | 8 + arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++ drivers/gpio/gpio-mvebu.c | 165 +++++++++++------- 4 files changed, 124 insertions(+), 62 deletions(-)