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Wed, 20 Sep 2023 13:52:37 -0700 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v4 0/2] iommu/arm-smmu-v3: Allow default substream bypass with a pasid support Date: Wed, 20 Sep 2023 13:52:02 -0700 Message-ID: X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|IA1PR12MB7543:EE_ X-MS-Office365-Filtering-Correlation-Id: 601cc50d-ed5a-4738-cce9-08dbba1b8d48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: A4P+3zSto94vySv9gQuQZpSk8sAbszsXgfEAcKNz9soNZS/ldkuiCQFsJZtaQhWJkkHbLOvwISw+/yourRooU2kXoP9YJBNoj9rXWArjtWnfKkRC9DPDTrlFeRtMjpbe0BVgxYz2UrikOtz0RLUYllsgmpBLym1YJ8fcsJEK5mjHP1z+3VMEzfw/V4ohIKw8xdS1x+SxIAXiGnFlLq+vZYma6JmcYiDInp0+TPGoVZY0JtzVQ3Ql+BFLGXcOouepz4uJvW3fhsBSg1RJd8ct7PK2VcSDLgsuVYmKOqsZ7QKx4FzrhH8AJXRLEWr0FXNn7OOx46BZwEyh1GS/pT/uAWpvxW//8keXjspuQlxWCse8gQX7RhPtgNb3hqSkdw/IrEx69ry+EOpedjAKd5g4FJj+pHB7xbT6pLeckXHnx9zZApnrkf8sWZk/eo2z2ZmHnFfgSUADRsyICG2BTtrmB/G+6Zy8XLUB7duFs1nEnOW/n+6oI3j9h7P8Z9PF4Y2dlZnixjKntavMZafQX5x7lN9oI8a4DlMM3YDjs4MCm67DW4smbhu0lTu02wytMHqDOlmomsqcCAKCIAYDHlYA7N4linvnrSlzg7r429hxXO8k8rF1WZNcRnNajOSmYbjjyIxhJmH6rnb3gQA9IAiaQPB8umWLA5N8qt7TOAobkizRqtHJvuCqPv1YFJ5aDhI+TLPrA0h0mGj7dYp5wBnka+avE+LalVPicaEoG465L3A7H5a0xCSxYzTC07OmWnFdCzxWS9DQ6OISe+GE6UHcRIax0Nyfc1BC5GsBg1C3hmNFSdPQarltVZU1fTo6pYPT X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(346002)(396003)(136003)(82310400011)(451199024)(186009)(1800799009)(36840700001)(46966006)(40470700004)(336012)(426003)(478600001)(41300700001)(40480700001)(2906002)(6666004)(356005)(966005)(70206006)(83380400001)(40460700003)(70586007)(54906003)(82740400003)(36756003)(7696005)(7636003)(110136005)(86362001)(2616005)(26005)(6636002)(316002)(4326008)(8676002)(8936002)(36860700001)(5660300002)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2023 20:52:49.8424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 601cc50d-ed5a-4738-cce9-08dbba1b8d48 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7543 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_135300_468048_E08C1FD4 X-CRM114-Status: GOOD ( 12.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org (This series is rebased on top of Michael's refactor series [1]) When an iommu_domain is set to IOMMU_DOMAIN_IDENTITY, the driver sets the arm_smmu_domain->stage to ARM_SMMU_DOMAIN_BYPASS and skips the allocation of a CD table, and then sets STRTAB_STE_0_CFG_BYPASS to the CONFIG field of the STE. This works well for devices that only have one substream, i.e. pasid disabled. With a pasid-capable device, however, there could be a use case where it allows an IDENTITY domain attachment without disabling its pasid feature. This requires the driver to allocate a multi-entry CD table to attach the IDENTITY domain to its default substream and to configure the S1DSS filed of the STE to STRTAB_STE_1_S1DSS_BYPASS. So, there is a missing link here between the STE setup and an IDENTITY domain attachment. This series fills the gap for the use case above. The first patch corrects the conditions at ats_enabled capability and arm_smmu_alloc_cd_tables() so that the use case above could set the ats_enabled and allocate a CD table correctly. The second patch reworks the arm_smmu_write_strtab_ent() in a fashion of all possible configurations of STE.Config fields. [1] https://lore.kernel.org/all/20230915132051.2646055-1-mshavit@google.com/ --- Changelog v4: * Rebased on top of v6.6-rc2 and Michael's refactor series v8 [1] v3: https://lore.kernel.org/all/cover.1692959239.git.nicolinc@nvidia.com/ * Replaced ARM_SMMU_DOMAIN_BYPASS_S1DSS with two boolean flags to correct conditions of STE bypass and CD table allocation. * Reworked arm_smmu_write_strtab_ent() with four helper functions v2: https://lore.kernel.org/all/20230817042135.32822-1-nicolinc@nvidia.com/ * Rebased on top of Michael's series reworking CD table ownership * Added a new ARM_SMMU_DOMAIN_BYPASS_S1DSS stage to tag the use case v1: https://lore.kernel.org/all/20230627033326.5236-1-nicolinc@nvidia.com/ Nicolin Chen (2): iommu/arm-smmu-v3: Add boolean bypass_ste and skip_cdtab flags iommu/arm-smmu-v3: Refactor arm_smmu_write_strtab_ent() drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 232 ++++++++++++-------- 1 file changed, 137 insertions(+), 95 deletions(-) base-commit: 8bab08e86afa9e0afd25887c0c273c1506d16c0f