Show patches with: Submitter = Andrea Merello       |    State = Action Required       |   28 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,2/2] arm: zynq: don't disable CONFIG_ARM_GLOBAL_TIMER due to CONFIG_CPU_FREQ anymore Fix missing entropy on Zynq arch due to get_cycles() not supported - - - --- 2021-04-06 Andrea Merello New
[v2,1/2] clocksource: arm_global_timer: implement rate compensation whenever source clock changes Fix missing entropy on Zynq arch due to get_cycles() not supported - 1 - --- 2021-04-06 Andrea Merello New
[2/2] arm: zynq: don't disable CONFIG_ARM_GLOBAL_TIMER due to CONFIG_CPU_FREQ anymore Fix missing entropy on Zynq arch due to get_cycles() not supported - - - --- 2021-02-17 Andrea Merello New
[1/2] clocksource: arm_global_timer: implement rate compensation whenever source clock changes Fix missing entropy on Zynq arch due to get_cycles() not supported - - - --- 2021-02-17 Andrea Merello New
[v5,7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - - - --- 2018-09-07 Andrea Merello New
[v5,6/7] dt-bindings: dmaengine: xilinx_dma: drop has-sg property [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - 2 - --- 2018-09-07 Andrea Merello New
[v5,5/7] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - 1 - --- 2018-09-07 Andrea Merello New
[v5,4/7] dmaengine: xilinx_dma: program hardware supported buffer length [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - - - --- 2018-09-07 Andrea Merello New
[v5,3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx, sg-length-width property [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - 2 - --- 2018-09-07 Andrea Merello New
[v5,2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - 1 - --- 2018-09-07 Andrea Merello New
[v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation [v5,1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation - - - --- 2018-09-07 Andrea Merello New
[v3,5/5] dt-bindings: dmaengine: xilinx_dma: drop has-sg property - 2 - --- 2018-06-25 Andrea Merello New
[v3,4/5] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather - 1 - --- 2018-06-25 Andrea Merello New
[v3,3/5] dmaengine: xilinx_dma: program hardware supported buffer length - - - --- 2018-06-25 Andrea Merello New
[v3,2/5] dt-bindings: dmaengine: xilinx_dma: add optional xlnx, sg-length-width property - 1 - --- 2018-06-25 Andrea Merello New
[v3,1/5] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors - 1 - --- 2018-06-25 Andrea Merello New
[v2,5/5] dt-bindings: xilinx_dma: drop has-sg property - - - --- 2018-06-21 Andrea Merello New
[v2,4/5] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather - - - --- 2018-06-21 Andrea Merello New
[v2,3/5] dmaengine: xilinx_dma: program hardware supported buffer length - - - --- 2018-06-21 Andrea Merello New
[v2,2/5] dt-bindings: xilinx_dma: add optional xlnx, sg-length-width property - - - --- 2018-06-21 Andrea Merello New
[v2,1/5] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors - - - --- 2018-06-21 Andrea Merello New
[6/6] dt-bindings: xilinx_dma: drop has-sg property - - - --- 2018-06-20 Andrea Merello New
[5/6] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather - - - --- 2018-06-20 Andrea Merello New
[4/6] dmaengine: xilinx_dma: fix hardcoded maximum transfer length may be wrong - - - --- 2018-06-20 Andrea Merello New
[3/6] dt-bindings: xilinx_dma: add required xlnx, lengthregwidth property - - - --- 2018-06-20 Andrea Merello New
[2/6] dmaengine: xilinx_dma: fix completion callback is not invoked for each DMA operation - - - --- 2018-06-20 Andrea Merello New
[1/6] dmaengine: xilinx_dma: fix splitting transfer causes misalignments - - - --- 2018-06-20 Andrea Merello New
clk: stm32f4: don't assume 48MHz clock is derived from primary PLL - - - --- 2016-09-08 Andrea Merello New