From patchwork Tue Nov 20 07:29:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cho KyongHo X-Patchwork-Id: 1771481 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 6E5DD3FC5A for ; Tue, 20 Nov 2012 07:33:16 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TaiIO-0003Gx-G6; Tue, 20 Nov 2012 07:31:00 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TaiHS-0002wt-M5 for linux-arm-kernel@lists.infradead.org; Tue, 20 Nov 2012 07:30:04 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MDR00J6AZHR41P0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 20 Nov 2012 16:29:59 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.47]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 92.AD.12699.7713BA05; Tue, 20 Nov 2012 16:29:59 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-1f-50ab31772ecd Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id F0.AD.12699.7713BA05; Tue, 20 Nov 2012 16:29:59 +0900 (KST) Received: from DOPULLIPCHO06 ([12.23.118.152]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDR009IZZHZT410@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 20 Nov 2012 16:29:59 +0900 (KST) From: Cho KyongHo To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/12] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU Date: Tue, 20 Nov 2012 16:29:59 +0900 Message-id: <001c01cdc6f0$d8d3c3e0$8a7b4ba0$%cho@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac3G8Ni8dPnlPyM6ReGWVy5qsjG0gg== Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsVy+t8zfd1yw9UBBmee6VpsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6MbTMzCj7KVDyeM4e9gXGaWBcjJ4eEgInE/zXLWCFsMYkL99az dTFycQgJLGOU6F97kAWm6NjyFiaIxHRGid3/DrNDOMuZJJ40bWAHqWIT0JJYPfc4I0hCRKCX UeJC/1ewFmaBH4wSi9+8YQapEhYIkVjx9gOYzSKgKjFr0y2w5bwCthKvps5ig7AFJX5Mvge2 mxlo6vqdx5kgbHmJzWveAvVyAN2kLvHory5IWERAT+Ju131WiBIRiX0v3jFCjBeQ+Db5EAtE uazEpgPMIOdICHSzS2xZep0d4jVJiYMrbrBMYBSbhWTzLCSbZyHZPAvJigWMLKsYRVMLkguK k9JzjfSKE3OLS/PS9ZLzczcxQqJFegfjqgaLQ4wCHIxKPLwPE1YFCLEmlhVX5h5ilOBgVhLh bSoHCvGmJFZWpRblxxeV5qQWH2L0Abp8IrOUaHI+MJLzSuINjY1NzExMTcwtTc1NcQgrifM2 e6QECAmkJ5akZqemFqQWwYxj4uCUamAUyLL/6Wq35Okq9+KgBJbjtya9f86mrf3GOihgUkXb 7/0nl4uv+cYo8mSuTFfnRa3qHyusDbZwZRks45u121tKfu/CrbwxsWHWMiyOLrMf1Dl3T/N/ Hb7WvHP7wSNtQnPkldfwrA0JZDH8qflom+/p0gsxeRf/Ce/WnnH76bU1+0U5d9kZcIYqsRRn JBpqMRcVJwIAGiOPZcMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPIsWRmVeSWpSXmKPExsVy+t9jQd1yw9UBBsf7NS02Pb7G6sDosXlJ fQBjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxraZGQUfZSoez5nD3sA4 TayLkZNDQsBE4tjyFiYIW0ziwr31bF2MXBxCAtMZJXb/O8wO4SxnknjStIEdpIpNQEti9dzj jCAJEYFeRokL/V+ZQBxmgR+MEovfvGEGqRIWCJFY8fYDmM0ioCoxa9MtVhCbV8BW4tXUWWwQ tqDEj8n3WEBsZqCp63ceZ4Kw5SU2r3kL1MsBdJO6xKO/uiBhEQE9ibtd91khSkQk9r14xziB UWAWkkmzkEyahWTSLCQtCxhZVjGKphYkFxQnpeca6RUn5haX5qXrJefnbmIEx+Iz6R2Mqxos DjEKcDAq8fA+TFgVIMSaWFZcmXuIUYKDWUmEt6kcKMSbklhZlVqUH19UmpNafIjRB+jRicxS osn5wDSRVxJvaGxiZmRpZGZhZGJujkNYSZy32SMlQEggPbEkNTs1tSC1CGYcEwenVAOj4IkV 70Olf7JdTy84Lh9s6C3fPePzjbnzpN+Wihw6wBK53vht0MPTa2L/uUut+720PmqV3CKP25HF 9kuzdy/OY4w1P7xnxfMSYZZl1Rc2vL+QniKvWxRsfeWuUbzCT6GWioStbP/aP4ls9G6Y3L/V bfp+bk35Ux8M1QLaZpwy2/+04/1cXy1bJZbijERDLeai4kQA7FS9uPICAAA= X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121120_023003_031482_9F225967 X-CRM114-Status: GOOD ( 10.28 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 HDRS_LCASE Odd capitalization of message header 0.0 T_MANY_HDRS_LCASE Odd capitalization of multiple message headers Cc: 'Kukjin Kim' , prathyush.k@samsung.com, 'Joerg Roedel' , sw0312.kim@samsung.com, 'Subash Patel' , 'Sanghyun Lee' , rahul.sharma@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Touching some System MMU needs its master devices' clock to be enabled before. This commit adds clk_ops.set_parent of gating clocks of System MMU to ensure gating clocks of System MMU's mater devices are enabled when enabling gating clocks of System MMU. Signed-off-by: KyongHo Cho --- arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 9e815ae..9dfb845 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -613,6 +613,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = { .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, }; +static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + return 0; +} + +static struct clk_ops exynos5_gate_clk_ops = { + .set_parent = exynos5_gate_clk_set_parent +}; + static struct clk exynos5_init_clocks_off[] = { { .name = "timers", @@ -854,76 +864,91 @@ static struct clk exynos5_init_clocks_off[] = { .name = "sysmmu", .devname = "exynos-sysmmu.0", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 1), }, { .name = "sysmmu", .devname = "exynos-sysmmu.1", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 2), }, { .name = "sysmmu", .devname = "exynos-sysmmu.2", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9) }, { .name = "sysmmu", .devname = "exynos-sysmmu.3", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.4", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 6) }, { .name = "sysmmu", .devname = "exynos-sysmmu.5", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.6", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.7", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9), }, { .name = "sysmmu", .devname = "exynos-sysmmu.8", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 10), }, { .name = "sysmmu", .devname = "exynos-sysmmu.9", .enable = &exynos5_clk_ip_isp0_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0x3F << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.10", .enable = &exynos5_clk_ip_isp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0xF << 4), }, { .name = "sysmmu", .devname = "exynos-sysmmu.11", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8) }, { .name = "sysmmu", .devname = "exynos-sysmmu.12", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 11), }, { .name = "sysmmu", .devname = "exynos-sysmmu.13", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 12), }, { .name = "sysmmu", .devname = "exynos-sysmmu.14", .enable = &exynos5_clk_ip_acp_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7) } };