From patchwork Wed Nov 14 08:51:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cho KyongHo X-Patchwork-Id: 1739951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id CB04D3FCF7 for ; Wed, 14 Nov 2012 08:53:54 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TYYhT-00037v-Ml; Wed, 14 Nov 2012 08:51:59 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TYYh8-00030E-EV for linux-arm-kernel@lists.infradead.org; Wed, 14 Nov 2012 08:51:42 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MDG008PUZ8CE130@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 14 Nov 2012 17:51:04 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.48]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 48.F6.12699.87B53A05; Wed, 14 Nov 2012 17:51:04 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-f2-50a35b78e342 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 97.F6.12699.87B53A05; Wed, 14 Nov 2012 17:51:04 +0900 (KST) Received: from DOPULLIPCHO06 ([12.23.118.152]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDG00HMRZ94QG40@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 14 Nov 2012 17:51:04 +0900 (KST) From: Cho KyongHo To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU Date: Wed, 14 Nov 2012 17:51:04 +0900 Message-id: <002201cdc245$2e05dac0$8a119040$%cho@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac3CRS3lHSVf47EGS3yhmPmjuO+Ylw== Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDIsWRmVeSWpSXmKPExsVy+t8zA92K6MUBBif2aVpsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6MbTMzCj7KVDyeM4e9gXGaWBcjJ4eEgInE6ZX72SFsMYkL99az gdhCAssYJZZNC4Kp+XPrOWMXIxdQfDqjRMPXb6wQRcuZJLoPaYDYbAJaEqvnHgcrEhHoZZS4 0P+VCcRhFnjAKLHi8EMmkCphAV+J23u2MHcxcnCwCKhK7HuoDRLmFbCVmHrsAzOELSjxY/I9 FhCbGWjo+p3HmSBseYnNa96CtUoIqEs8+qsLEhYR0JP4ePMqO0SJiMS+F+8YQWwWAQGJb5MP sUCUy0psOsAM8Us/u8TVQwIQtqTEwRU3WCYwis1CsngWksWzkCyehWTDAkaWVYyiqQXJBcVJ 6blGesWJucWleel6yfm5mxghUSK9g3FVg8UhRgEORiUe3oD+RQFCrIllxZW5hxglOJiVRHhj rRYHCPGmJFZWpRblxxeV5qQWH2L0ATp8IrOUaHI+MILzSuINjY1NzExMTcwtTc1NcQgrifM2 e6QECAmkJ5akZqemFqQWwYxj4uCUamBcGe7qb/FiccZL3TD1l55v2FaELl3aOscjMfzqvR3y IUod/c4K0y3EV9qq8m5z3LdH96dZ2+aKey+3LGpITLo0fU5VUuXUq0ava9VK7swqLPvctb/m XtKb4y0p3B7T5y1oWS5xNbRC/WrmBLt7PZGKxrXzOMKr5s2Jf5cTsZbFRcvbfuI3zkQlluKM REMt5qLiRAD1cw4WvwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jQd2K6MUBBouvq1hsenyN1YHRY/OS +gDGqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg qUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwjrGjG0zMwo+ylQ8njOHvYFx mlgXIyeHhICJxJ9bzxkhbDGJC/fWs3UxcnEICUxnlGj4+o0VJCEksJxJovuQBojNJqAlsXru cUaQIhGBXkaJC/1fmUAcZoEHjBIrDj9kAqkSFvCVuL1nC3MXIwcHi4CqxL6H2iBhXgFbianH PjBD2IISPybfYwGxmYGGrt95nAnClpfYvOYtWKuEgLrEo7+6IGERAT2JjzevskOUiEjse/GO cQKjwCwkk2YhmTQLyaRZSFoWMLKsYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiOw2fSOxhX NVgcYhTgYFTi4Q3oXxQgxJpYVlyZe4hRgoNZSYQ31mpxgBBvSmJlVWpRfnxRaU5q8SFGH6A/ JzJLiSbnA1NEXkm8obGJmZGlkZmFkYm5OQ5hJXHeZo+UACGB9MSS1OzU1ILUIphxTBycUg2M nt+7tTrCSzXvb1oka/AkpVnxeuWaFj+hqQeZJwSfMrZRX/Wq5se9Dzv18ve9+jPPZblZzQS2 v2fUxOz3H1SUvndbImtC6Jk3EU5KXXG/jn9VlDn65ETG6Ule0+q36B1+rVDDfkDEVfV5YvNx Xs6MiBsXfilu1Zw070zchEWJ3x/PFgl5vD15qxJLcUaioRZzUXEiAEY+9VzwAgAA X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121114_035139_062659_C21B3D36 X-CRM114-Status: GOOD ( 10.68 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.34 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 HDRS_LCASE Odd capitalization of message header 0.0 T_MANY_HDRS_LCASE Odd capitalization of multiple message headers Cc: 'Kukjin Kim' , prathyush.k@samsung.com, 'Joerg Roedel' , 'Subash Patel' , 'Sanghyun Lee' , rahul.sharma@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Touching some System MMU needs its master devices' clock to be enabled before. This commit adds clk_ops.set_parent of gating clocks of System MMU to ensure gating clocks of System MMU's mater devices are enabled when enabling gating clocks of System MMU. Signed-off-by: KyongHo Cho --- arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 9e815ae..9dfb845 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -613,6 +613,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = { .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, }; +static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + return 0; +} + +static struct clk_ops exynos5_gate_clk_ops = { + .set_parent = exynos5_gate_clk_set_parent +}; + static struct clk exynos5_init_clocks_off[] = { { .name = "timers", @@ -854,76 +864,91 @@ static struct clk exynos5_init_clocks_off[] = { .name = "sysmmu", .devname = "exynos-sysmmu.0", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 1), }, { .name = "sysmmu", .devname = "exynos-sysmmu.1", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 2), }, { .name = "sysmmu", .devname = "exynos-sysmmu.2", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9) }, { .name = "sysmmu", .devname = "exynos-sysmmu.3", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.4", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 6) }, { .name = "sysmmu", .devname = "exynos-sysmmu.5", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.6", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.7", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9), }, { .name = "sysmmu", .devname = "exynos-sysmmu.8", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 10), }, { .name = "sysmmu", .devname = "exynos-sysmmu.9", .enable = &exynos5_clk_ip_isp0_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0x3F << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.10", .enable = &exynos5_clk_ip_isp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0xF << 4), }, { .name = "sysmmu", .devname = "exynos-sysmmu.11", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8) }, { .name = "sysmmu", .devname = "exynos-sysmmu.12", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 11), }, { .name = "sysmmu", .devname = "exynos-sysmmu.13", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 12), }, { .name = "sysmmu", .devname = "exynos-sysmmu.14", .enable = &exynos5_clk_ip_acp_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7) } };