From patchwork Thu Nov 22 11:32:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cho KyongHo X-Patchwork-Id: 1783501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 11379DF230 for ; Thu, 22 Nov 2012 11:36:43 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbV29-0006YW-1y; Thu, 22 Nov 2012 11:33:29 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbV1z-0006W9-U7 for linux-arm-kernel@lists.infradead.org; Thu, 22 Nov 2012 11:33:22 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MDW00GHW01YO9P0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 22 Nov 2012 20:32:30 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 7B.C7.12699.E4D0EA05; Thu, 22 Nov 2012 20:32:30 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-ef-50ae0d4ea8ed Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 4B.C7.12699.E4D0EA05; Thu, 22 Nov 2012 20:32:30 +0900 (KST) Received: from DOPULLIPCHO06 ([12.23.118.152]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDW00H0Z026FU90@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 22 Nov 2012 20:32:30 +0900 (KST) From: Cho KyongHo To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/12] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU Date: Thu, 22 Nov 2012 20:32:30 +0900 Message-id: <002201cdc8a5$0e9fb8c0$2bdf2a40$%cho@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac3IpQ5zVIVC2V4yTPGz75JnGFmJVA== Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsVy+t8zY10/3nUBBt2rlS02Pb7G6sDosXlJ fQBjFJdNSmpOZllqkb5dAlfGz2sbGQveyla8+BDbwLhBvIuRk0NCwESiY/J9JghbTOLCvfVs XYxcHEICyxgl7veuZ4Yp6v5/ihHEFhJYxChxaII/RNFyJon5G7aBJdgEtCRWzz3OCJIQEehl lLjQ/xVsrLBAiMSbhulgNouAqsTPTQdYQWxeAVuJOWvWsEDYghI/Jt8Ds5mBBq3feZwJwpaX 2LzmLdAVHEBXqEs8+qsLEhYR0JO4tqMTqkREYt+Ld4wQ4wUkvk0+xAJRLiux6QAzyDkSAr/Z JKZtW8oO8YykxMEVN1gmMIrOQrJ5FpLNs5BsnoVkxQJGllWMoqkFyQXFSem5RnrFibnFpXnp esn5uZsYIREhvYNxVYPFIUYBDkYlHt4Mg7UBQqyJZcWVuYcYJTiYlUR473GvCxDiTUmsrEot yo8vKs1JLT7E6AN0+URmKdHkfGC05pXEGxobm5iZmJqYW5qam+IQVhLnbfZICRASSE8sSc1O TS1ILYIZx8TBKdXAGNTzfNXPrp95FobdrYt1XDe2B0offXT80QPz1wa2UyzXta28yp1hxrNd Ja/1QsQBts2TOFRlF1/99eaxzHNGr0ieyIO8eu/mKbo0rro2+7THnfcv3J9z2nYmxr6UW5yW 3PNfocx895x5R8x2zEvPNO9jY7bw2+uR/0Qny9E7qesmu1GrZvMSJZbijERDLeai4kQAqRPy l7UCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrIIsWRmVeSWpSXmKPExsVy+t9jAV0/3nUBBk+vy1tsenyN1YHRY/OS +gDGqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg qUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwjrGjJ/XNjIWvJWtePEhtoFx g3gXIyeHhICJRPf/U4wQtpjEhXvr2UBsIYFFjBKHJvh3MXIB2cuZJOZv2AZWxCagJbF67nFG kISIQC+jxIX+r0wgCWGBEIk3DdPBbBYBVYmfmw6wgti8ArYSc9asYYGwBSV+TL4HZjMDDVq/ 8zgThC0vsXnNW+YuRg6gK9QlHv3VBQmLCOhJXNvRCVUiIrHvxTvGCYz8s5BMmoVk0iwkk2Yh aVnAyLKKUTS1ILmgOCk910ivODG3uDQvXS85P3cTIzjenknvYFzVYHGIUYCDUYmHN8NgbYAQ a2JZcWXuIUYJDmYlEd573OsChHhTEiurUovy44tKc1KLDzH6AD06kVlKNDkfmArySuINjU3M jCyNzCyMTMzNcQgrifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamDsE5vIkrw7mtl/3rFtD5nN 9/ZzMBiX8c3lni/74ppF39TFk3ad+vhBcmNYSfVsV8mfm/9tDw+drfJzV/gTIc0UtQ1iCge0 nYPvijTWSYd+KTAtKDw/b/I89nxN0T0JHyTLFu4LvaPs0WxpxDd/0qlp97kWrb6uXSzgVad0 UXNV/83PEr8e/9BVYinOSDTUYi4qTgQAU761aOQCAAA= X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121122_063320_532661_74EA1F2D X-CRM114-Status: GOOD ( 10.05 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 HDRS_LCASE Odd capitalization of message header 0.0 T_MANY_HDRS_LCASE Odd capitalization of multiple message headers X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Touching some System MMU needs its master devices' clock to be enabled before. This commit adds clk_ops.set_parent of gating clocks of System MMU to ensure gating clocks of System MMU's mater devices are enabled when enabling gating clocks of System MMU. Signed-off-by: KyongHo Cho --- arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index e48d7c2..a86e88e 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -614,6 +614,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = { .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, }; +static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + return 0; +} + +static struct clk_ops exynos5_gate_clk_ops = { + .set_parent = exynos5_gate_clk_set_parent +}; + static struct clk exynos5_init_clocks_off[] = { { .name = "timers", @@ -855,71 +865,85 @@ static struct clk exynos5_init_clocks_off[] = { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 1), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1), .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 2), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9) }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 6) }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 10), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), .enable = &exynos5_clk_ip_isp0_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0x3F << 8), }, { .name = SYSMMU_CLOCK_NAME2, .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), .enable = &exynos5_clk_ip_isp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0xF << 4), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 11), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13), .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 12), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(2d, 14), .enable = &exynos5_clk_ip_acp_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7) } };