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Wed, 21 Nov 2012 14:03:18 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.49]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id EF.B8.12699.6906CA05; Wed, 21 Nov 2012 14:03:18 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-81-50ac609646ae Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3F.B8.12699.6906CA05; Wed, 21 Nov 2012 14:03:18 +0900 (KST) Received: from DOPULLIPCHO06 ([12.23.118.152]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDT00NNSNDI0B70@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 21 Nov 2012 14:03:18 +0900 (KST) From: Cho KyongHo To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/12] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU Date: Wed, 21 Nov 2012 14:03:18 +0900 Message-id: <002801cdc7a5$8535f6d0$8fa1e470$%cho@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac3HpYUaIEl+tOnhTL2nVMjbCCI2Tw== Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsVy+t8zQ91pCWsCDK7fkbLY9PgaqwOjx+Yl 9QGMUVw2Kak5mWWpRfp2CVwZv7YdYSlYLlsx+X95A+NJsS5GTg4JAROJy38OMULYYhIX7q1n 62Lk4hASWMYoser/KdYuRg6wohO/uSDi0xklZp78wAThLGeSeNN0kwWkm01AS2L13OOMIAkR gV5GiQv9X8GqmAV+MEosfvOGGaRKWCBEouF1HxuIzSKgKvFzyz5WEJtXwFZi84w1zBC2oMSP yffApjIDTV2/8zgThC0vsXnNW2aIk9QlHv3VBQmLCOhJbPn7mRWiRERi34t3jBDjBSS+TT7E AlEuK7HpADPIORIC3ewS2z4uYoV4WVLi4IobLBMYxWYh2TwLyeZZSDbPQrJiASPLKkbR1ILk guKk9FwjveLE3OLSvHS95PzcTYyQWJHewbiqweIQowAHoxIPr8S+1QFCrIllxZW5hxglOJiV RHgZ5NcECPGmJFZWpRblxxeV5qQWH2L0Abp8IrOUaHI+MI7zSuINjY1NzExMTcwtTc1NcQgr ifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamCsDWPt4DQ//Yztb0JWrBdHmNKBaBmpvoWlazv7 HXadErvs+WKzr4L6618zl8xjPJXf4VWxTTnkxy5em2fNF8TsOIzPxPi72KRzGZz+uuNAlFhG tOD3tS48u9rWlhzX7wgOa3vIVvr/LkdV0JMMFfvZ3Io/mUQsXcP/KJ6vzPdTy93iZ5/DqMRS nJFoqMVcVJwIADN7K5TCAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHIsWRmVeSWpSXmKPExsVy+t9jQd1pCWsCDB7OELPY9PgaqwOjx+Yl 9QGMUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlA U5UUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhHWMGb+2HWEpWC5bMfl/eQPj SbEuRg4OCQETiRO/uboYOYFMMYkL99azdTFycQgJTGeUmHnyAxOEs5xJ4k3TTRaQKjYBLYnV c48zgiREBHoZJS70fwWrYhb4wSix+M0bZpAqYYEQiYbXfWwgNouAqsTPLftYQWxeAVuJzTPW MEPYghI/Jt8Dm8oMNHX9zuNMELa8xOY1b5khzlOXePRXFyQsIqAnseXvZ1aIEhGJfS/eMU5g FJiFZNIsJJNmIZk0C0nLAkaWVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjBkfhMegfjqgaL Q4wCHIxKPLwS+1YHCLEmlhVX5h5ilOBgVhLhZZBfEyDEm5JYWZValB9fVJqTWnyI0Qfo0YnM UqLJ+cAkkVcSb2hsYmZkaWRmYWRibo5DWEmct9kjJUBIID2xJDU7NbUgtQhmHBMHp1QDY8Ok /5Y3I6OOfVnNPy/rMK+PlvKhLZNT94l4z2y44PL0Bm9P6X/NMJ+LPeannZ4cFTrwj03nwC7d zrgFMj675700WrzX+v7cJTIe3nwx+im6d6Zb71K+4nnoSFyHPItq0KS/2zgUzDZFBV/nZBGZ fH9tdKp+Zv7EQtXqqacZWX8e3lum8WbhdSWW4oxEQy3mouJEAFolX6bxAgAA X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121121_000321_542964_58385804 X-CRM114-Status: GOOD ( 10.43 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 HDRS_LCASE Odd capitalization of message header 0.0 T_MANY_HDRS_LCASE Odd capitalization of multiple message headers Cc: 'Kukjin Kim' , prathyush.k@samsung.com, 'Joerg Roedel' , sw0312.kim@samsung.com, 'Subash Patel' , 'Sanghyun Lee' , rahul.sharma@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Touching some System MMU needs its master devices' clock to be enabled before. This commit adds clk_ops.set_parent of gating clocks of System MMU to ensure gating clocks of System MMU's mater devices are enabled when enabling gating clocks of System MMU. Change-Id: Icd58b12f599e92692c032516331a444f4703ba6b Signed-off-by: KyongHo Cho --- arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 9e815ae..9dfb845 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -613,6 +613,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = { .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, }; +static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + return 0; +} + +static struct clk_ops exynos5_gate_clk_ops = { + .set_parent = exynos5_gate_clk_set_parent +}; + static struct clk exynos5_init_clocks_off[] = { { .name = "timers", @@ -854,76 +864,91 @@ static struct clk exynos5_init_clocks_off[] = { .name = "sysmmu", .devname = "exynos-sysmmu.0", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 1), }, { .name = "sysmmu", .devname = "exynos-sysmmu.1", .enable = &exynos5_clk_ip_mfc_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 2), }, { .name = "sysmmu", .devname = "exynos-sysmmu.2", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9) }, { .name = "sysmmu", .devname = "exynos-sysmmu.3", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.4", .enable = &exynos5_clk_ip_gen_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 6) }, { .name = "sysmmu", .devname = "exynos-sysmmu.5", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7), }, { .name = "sysmmu", .devname = "exynos-sysmmu.6", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.7", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 9), }, { .name = "sysmmu", .devname = "exynos-sysmmu.8", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 10), }, { .name = "sysmmu", .devname = "exynos-sysmmu.9", .enable = &exynos5_clk_ip_isp0_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0x3F << 8), }, { .name = "sysmmu", .devname = "exynos-sysmmu.10", .enable = &exynos5_clk_ip_isp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (0xF << 4), }, { .name = "sysmmu", .devname = "exynos-sysmmu.11", .enable = &exynos5_clk_ip_disp1_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 8) }, { .name = "sysmmu", .devname = "exynos-sysmmu.12", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 11), }, { .name = "sysmmu", .devname = "exynos-sysmmu.13", .enable = &exynos5_clk_ip_gscl_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 12), }, { .name = "sysmmu", .devname = "exynos-sysmmu.14", .enable = &exynos5_clk_ip_acp_ctrl, + .ops = &exynos5_gate_clk_ops, .ctrlbit = (1 << 7) } };