From patchwork Wed Jul 1 13:36:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 6703651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4C1E59F380 for ; Wed, 1 Jul 2015 13:39:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B1D2206D6 for ; Wed, 1 Jul 2015 13:39:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B61D20648 for ; Wed, 1 Jul 2015 13:39:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZAIC1-00081T-RP; Wed, 01 Jul 2015 13:36:49 +0000 Received: from mailout4.w1.samsung.com ([210.118.77.14]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZAIBy-0007v3-Rd for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2015 13:36:47 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NQT00ETD9SNQ100@mailout4.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2015 14:36:23 +0100 (BST) X-AuditID: cbfec7f4-f79c56d0000012ee-ee-5593ecd6d4e7 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id AA.93.04846.6DCE3955; Wed, 1 Jul 2015 14:36:23 +0100 (BST) Received: from fedinw7x64 ([106.109.131.169]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NQT00BCE9SMRG40@eusync3.samsung.com>; Wed, 01 Jul 2015 14:36:22 +0100 (BST) From: Pavel Fedin To: 'Robert Richter' , 'Marc Zygnier' , 'Thomas Gleixner' , 'Jason Cooper' References: <1435673643-31676-1-git-send-email-rric@kernel.org> <1435673643-31676-5-git-send-email-rric@kernel.org> In-reply-to: <1435673643-31676-5-git-send-email-rric@kernel.org> Subject: RE: [PATCH 4/4] irqchip, gicv3-its: Implement Cavium ThunderX errata 22375, 24313 Date: Wed, 01 Jul 2015 16:36:22 +0300 Message-id: <023101d0b402$eba41e00$c2ec5a00$@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Outlook 14.0 Thread-index: AQGgDVz+LB94cX2dQtr7QruH9SNYqQGkL/+AnhrHpqA= Content-language: ru X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4Vd3rbyaHGvxys2hccpnFYtPja6wW f+/8Y7M4uGojk8W3T++YLBoP+1ps3jSV2YHdY828NYweM34vYvHYtKqTzaPhwHkWj3fnzrF7 bF5SH8AWxWWTkpqTWZZapG+XwJXx4d8WtoI5QhUTPoo0ML7g62Lk5JAQMJH4+usvE4QtJnHh 3nq2LkYuDiGBpYwSj1r+sUM43xklOicfYAapYhNQlzj99QMLSEJEYB6jxLeOX2BVzAItjBIH djwGqxISKJXYtO8F0FwODk4BB4nLr1NAwsICMRKnPrxiBgmzCKhK3J7BCRLmFbCU+P79OBOE LSjxY/I9FhCbWUBLYv1OiDizgLzE5jVvmSEuVZDYcfY1I4gtImAl8WrCA2aIGhGJaf/uMU9g FJqFZNQsJKNmIRk1C0nLAkaWVYyiqaXJBcVJ6bmGesWJucWleel6yfm5mxghMfNlB+PiY1aH GAU4GJV4eAXEJocKsSaWFVfmHmKU4GBWEuGd+RooxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfu rvchQgLpiSWp2ampBalFMFkmDk6pBsakOdXX3hcurkuM9HJh0vv42mS30De34KrgDcdvGXKc q/v25+qK6EtNn6/O+GKsuODwnCo9Q/WE+/URIcufLam49u3f0tXVIgZyP01Kqndu/TzLNNUm UK1x+uR2rYf/9RksG6qc9B643zA7dpvlRrzMbJOtt2O5jt548GNNAvuWR1N+nixdnLlViaU4 I9FQi7moOBEAcVAofpUCAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150701_063647_045688_F52DB514 X-CRM114-Status: GOOD ( 14.32 ) X-Spam-Score: -7.5 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: 'Robert Richter' , 'Tirumalesh Chalamarla' , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello! > This implements two gicv3-its errata for ThunderX. Both with small > impact affecting only ITS table allocation. > > erratum 22375: only alloc 8MB table size I have a simpler solution to this one: --- For some reason on ThunderX GITS_BASER reports entry size == 8 for ITT, while real size, reported by GITS_TYPER is 4. Consequently, allocated table size appears twice bigger than expected. And, if we set GITS_BASER.SIZE accordingly (the value appears to be 0xFF instead of 0x7F) the ITS will not work. Signed-off-by: Pavel Fedin --- drivers/irqchip/irq-gic-v3-its.c | 3 ++- include/linux/irqchip/arm-gic-v3.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ed70163..c420f17 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -827,6 +827,7 @@ static int its_alloc_tables(struct its_node *its) if (type == GITS_BASER_TYPE_DEVICE) { u64 typer = readq_relaxed(its->base + GITS_TYPER); u32 ids = GITS_TYPER_DEVBITS(typer); + u32 itte_size = GITS_TYPER_ITTE_SIZE(typer); /* * 'order' was initialized earlier to the default page @@ -834,7 +835,7 @@ static int its_alloc_tables(struct its_node *its) * smaller than that. If the requested allocation * is smaller, round up to the default page granule. */ - order = max(get_order((1UL << ids) * entry_size), + order = max(get_order((1UL << ids) * itte_size), order); if (order >= MAX_ORDER) { order = MAX_ORDER - 1; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index ffbc034..7f515e6 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -184,6 +184,8 @@ #define GITS_CTLR_ENABLE (1U << 0) #define GITS_CTLR_QUIESCENT (1U << 31) +#define GITS_TYPER_ITTE_SIZE_SHIFT 4 +#define GITS_TYPER_ITTE_SIZE(r) ((((r) >> GITS_TYPER_ITTE_SIZE_SHIFT) & 0xf) + 1) #define GITS_TYPER_DEVBITS_SHIFT 13 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) #define GITS_TYPER_PTA (1UL << 19)