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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jEChEu3344BdHYPwyNpUg8OvRy/artJMWmV46zplrvk=; b=EQUgTqWeqIhDogj9D0/ZYuTSaZpTnx8R2Qki8fxG10HXW3crDLp5DgFeSE7V3XPIIv 2z2x4ItLzs297UXP7hpsFQ3kpSkKwcq2cVXlqPpFxkz5BilmCxZA4ZYiJ/LOCDameYYs WNdgZQfatYHvySuppP5lTmAU2Mkve1qMgH8FKJRzsTVENgTTtJmmn/MMRM3e6waiv70z hzixy1Jb5U6dd8hVcjzxZafx+3fZs9frdE1KKYCJhuOWeWmzknKDnEj2uK0rc3QmWpK6 9mF595FpNir6taTUSb7xM0LzxncIQgishPOkyvm/ioWUbzzH8Fd6FJhqPIbXCqKatKyq K3HQ== X-Gm-Message-State: AA+aEWYGZrnzmUWsMoMkm1MpUfp359GXKsIeJLxmFGDcwEJVxl0CGWkm nomULDVM5eIj2FW9iEuiu7c= X-Google-Smtp-Source: AFSGD/VS/IymxqJCJFFznwYQc1Sw+M/bg2M9AGSUNkXhnRCoaKJbBXXop29qHjUQqTAwnV9m5I0fZA== X-Received: by 2002:a5d:6684:: with SMTP id l4mr21290291wru.154.1543131835958; Sat, 24 Nov 2018 23:43:55 -0800 (PST) Received: from localhost.localdomain ([185.219.177.224]) by smtp.gmail.com with ESMTPSA id 6-v6sm12296780wmg.19.2018.11.24.23.43.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 24 Nov 2018 23:43:55 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [RFC PATCH v4 06/17] irqchip/sun4i: Move IC specific register offsets to struct Date: Sun, 25 Nov 2018 10:43:09 +0300 Message-Id: <0242923026be282e26fe9e50d9bb0ec3d5ae355f.1543131714.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181124_234407_726212_6B7036B3 X-CRM114-Status: GOOD ( 16.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mesih Kilinc , Julian Calaby , Linus Walleij , Daniel Lezcano , Russell King , Marc Zyngier , Chen-Yu Tsai , Rob Herring , Maxime Ripard , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves IC specific register offsets to sun4i_irq_chip_data struct in order to support different chips. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 0c32506..507f4e3 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -28,12 +28,16 @@ #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 struct sun4i_irq_chip_data { void __iomem *irq_base; struct irq_domain *irq_domain; + u32 enable_reg_offset; + u32 mask_reg_offset; }; static struct sun4i_irq_chip_data *irq_ic_data; @@ -57,9 +61,10 @@ static void sun4i_irq_mask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val & ~(1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static void sun4i_irq_unmask(struct irq_data *irqd) @@ -69,9 +74,10 @@ static void sun4i_irq_unmask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val | (1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static struct irq_chip sun4i_irq_chip = { @@ -105,20 +111,23 @@ static int __init sun4i_of_init(struct device_node *node, return -ENOMEM; } + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", node); /* Disable all interrupts */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2)); /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2)); /* Clear all the pending interrupts */ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));