From patchwork Thu Sep 1 09:09:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 9308629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E0592607D2 for ; Thu, 1 Sep 2016 09:12:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CDB97292AE for ; Thu, 1 Sep 2016 09:12:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C23D6292B1; Thu, 1 Sep 2016 09:12:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A4116292AE for ; Thu, 1 Sep 2016 09:12:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfO1F-0006RI-JX; Thu, 01 Sep 2016 09:10:45 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfO0R-0004ot-By for linux-arm-kernel@lists.infradead.org; Thu, 01 Sep 2016 09:09:58 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8199QYO027752; Thu, 1 Sep 2016 04:09:26 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8199PVj015226; Thu, 1 Sep 2016 04:09:25 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Thu, 1 Sep 2016 04:09:24 -0500 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8199CdS028084; Thu, 1 Sep 2016 04:09:22 -0500 From: Jyri Sarha To: , , , , Subject: [PATCH v4 3/8] drm/tilcdc: Add blue-and-red-crossed devicetree property Date: Thu, 1 Sep 2016 12:09:07 +0300 Message-ID: <097cda0d23741ab21aa13bd3f152ca2f32bf9ab3.1472719892.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160901_020955_587173_545846F9 X-CRM114-Status: GOOD ( 15.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: airlied@linux.ie, Jyri Sarha , tomi.valkeinen@ti.com, kbeldan@baylibre.com, laurent.pinchart@ideasonboard.com, daniel@ffwll.ch Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add "blue-and-red-wiring"-device tree property and update devicetree binding document. The red and blue components are reversed between 24 and 16 bit modes on am335x LCDC output pins. To get 24 RGB format the red and blue wires has to be crossed and this in turn causes 16 colors output to be in BGR format. With straight wiring the 16 color is RGB and 24 bit is BGR. The new property describes whether the red and blue wires are crossed or not. If the property is not present or its value is not recognized the legacy mode is assumed. The legacy configuration supports RGB565, RGB888 and XRGB8888 formats. However, depending on wiring, the red and blue colors are swapped in either 16 or 24-bit color modes. For more details see section 3.1.1 in AM335x Silicon Errata: http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 Signed-off-by: Jyri Sarha Acked-by: Rob Herring --- .../devicetree/bindings/display/tilcdc/tilcdc.txt | 22 ++++++++++++ drivers/gpu/drm/tilcdc/tilcdc_drv.c | 41 ++++++++++++++++++++++ drivers/gpu/drm/tilcdc/tilcdc_drv.h | 4 +++ drivers/gpu/drm/tilcdc/tilcdc_plane.c | 9 ++--- 4 files changed, 70 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt index 6efa4c5..a5007aa 100644 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt @@ -17,6 +17,18 @@ Optional properties: the lcd controller. - max-pixelclock: The maximum pixel clock that can be supported by the lcd controller in KHz. + - blue-and-red-wiring: Recognized values "default", "straight" or + "crossed". This property deals with the LCDC revision 2 (found on + AM335x) color errata [1]. + - "straight" indicates normal wiring that supports RGB565, + BGR888, and XBGR8888 color formats. + - "crossed" indicates wiring that has blue and red wires + crossed. This setup supports BGR565, RGB888 and XRGB8888 + formats. + - If the property is not present or its value is not recognized + the legacy mode is assumed. This configuration supports RGB565, + RGB888 and XRGB8888 formats. However, depending on wiring, the red + and blue colors are swapped in either 16 or 24-bit color modes. Optional nodes: @@ -28,6 +40,14 @@ Optional nodes: Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting tfp410 DVI encoder or lcd panel to lcdc +[1] There is an errata about AM335x color wiring. For 16-bit color mode + the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]), + but for 24 bit color modes the wiring of blue and red components is + crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is + for Blue[3-7]. For more details see section 3.1.1 in AM335x + Silicon Errata: + http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 + Example: fb: fb@4830e000 { @@ -37,6 +57,8 @@ Example: interrupts = <36>; ti,hwmods = "lcdc"; + blue-and-red-wiring = "crossed"; + port { lcdc_0: endpoint@0 { remote-endpoint = <&hdmi_0>; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index e45c268..ed4dc5c 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -33,6 +33,20 @@ static LIST_HEAD(module_list); +static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; + +static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, + DRM_FORMAT_BGR888, + DRM_FORMAT_XBGR8888 }; + +static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XRGB8888 }; + +static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XRGB8888 }; + void tilcdc_module_init(struct tilcdc_module *mod, const char *name, const struct tilcdc_module_ops *funcs) { @@ -318,6 +332,33 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) pm_runtime_put_sync(dev->dev); + if (priv->rev == 1) { + DBG("Revision 1 LCDC supports only RGB565 format"); + priv->pixelformats = tilcdc_rev1_formats; + priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); + } else { + const char *str = "\0"; + + of_property_read_string(node, "blue-and-red-wiring", &str); + if (0 == strcmp(str, "crossed")) { + DBG("Configured for crossed blue and red wires"); + priv->pixelformats = tilcdc_crossed_formats; + priv->num_pixelformats = + ARRAY_SIZE(tilcdc_crossed_formats); + } else if (0 == strcmp(str, "straight")) { + DBG("Configured for straight blue and red wires"); + priv->pixelformats = tilcdc_straight_formats; + priv->num_pixelformats = + ARRAY_SIZE(tilcdc_straight_formats); + } else { + DBG("Blue and red wiring '%s' unknown, use legacy mode", + str); + priv->pixelformats = tilcdc_legacy_formats; + priv->num_pixelformats = + ARRAY_SIZE(tilcdc_legacy_formats); + } + } + ret = modeset_init(dev); if (ret < 0) { dev_err(dev->dev, "failed to initialize mode setting\n"); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index 13001df..0e19c14 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -65,6 +65,10 @@ struct tilcdc_drm_private { */ uint32_t max_width; + /* Supported pixel formats */ + const uint32_t *pixelformats; + uint32_t num_pixelformats; + /* The context for pm susped/resume cycle is stored here */ struct drm_atomic_state *saved_state; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_plane.c b/drivers/gpu/drm/tilcdc/tilcdc_plane.c index 41911e3..74c65fa 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_plane.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_plane.c @@ -24,10 +24,6 @@ #include "tilcdc_drv.h" -static const u32 tilcdc_formats[] = { DRM_FORMAT_RGB565, - DRM_FORMAT_RGB888, - DRM_FORMAT_XRGB8888 }; - static struct drm_plane_funcs tilcdc_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -114,12 +110,13 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = { int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane) { + struct tilcdc_drm_private *priv = dev->dev_private; int ret; ret = drm_plane_init(dev, plane, 1, &tilcdc_plane_funcs, - tilcdc_formats, - ARRAY_SIZE(tilcdc_formats), + priv->pixelformats, + priv->num_pixelformats, true); if (ret) { dev_err(dev->dev, "Failed to initialize plane: %d\n", ret);