From patchwork Tue Nov 19 16:40:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 13880304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACE23D591A5 for ; Tue, 19 Nov 2024 16:53:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eCsrDZb/8rZtvR3JlohYSCZsiHt/QIIQSYMh0P5ZUhw=; b=H4RPwbz3rXt83T3eD7H8+fQzVa CSVVpL8b/J47Ki5TAccb0+tzmGJGkPLtGeJ3ZudqJUnp78xPdniFzuEIovK7p0hs97+D11/ap8KMS vr8A0hJe+oS81teCj6tDKlIKJhAoX35OlXJ+dMEUV0KmRLy25K0SLBTPmMuqmfuzUbHetySCZw6rd ZxLrHsz9X8ga6LdtfHk99P0j1pJAicOiO36n0Xt0CWwPy68tLxEs7FII3oH/GrYcsNSuad6zJQjG0 lYZxyfbOKivMcySARI/eBLkjTvHWlrN0iybEjlXg/zYw+WG6st6mLk034qbw7sq0j+0ZtqbJaIetx YAdd8fxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tDRTQ-0000000D6rR-083q; Tue, 19 Nov 2024 16:53:08 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tDRI3-0000000D3hP-0cmK for linux-arm-kernel@lists.infradead.org; Tue, 19 Nov 2024 16:41:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1732034483; x=1763570483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uSvcCWbA3Ht3nwAd4jpwfcx3sIAlsyNlUm64CZ1vwjo=; b=torysfvad1X5Tf27mJC2jOA/QhIXpDDPdBu3kSsJo3JwAM1VpRb9hwml TQx8NOr3FEBpMwXsGnNs8EqepZ7eBWZqrtzvOFyvKMSAq7Cqg6I3exqha YpZryC4/K2ce27qvooYMWbz3FVvjhveEUzyGi8BZqbXHNMiQL3HuZhtPU RzcmRFRRUPQ35OKeYLJWiGPdjFZAntmLlIrUgMy915Z7LzpNhEwqi+vmG viF3SvZyYm+ooCUePRYcVc/w6MCpzSfqb2X+btESXy2guXl4sGLu9JI+e IjcC1yCKScyzuP3gP8jxEvzVjRQVKWmLnbuLTzwVYlrGsrnCx+jswxI3z w==; X-CSE-ConnectionGUID: RxwVwqVBQ5Gt75b5OWvVzw== X-CSE-MsgGUID: BLlxpfozREyxy5M5U2FaWA== X-IronPort-AV: E=Sophos;i="6.12,166,1728975600"; d="scan'208";a="34239903" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Nov 2024 09:41:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 19 Nov 2024 09:40:55 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 19 Nov 2024 09:40:55 -0700 From: To: , , , , , , , , CC: , , , , , , , , , , , , Ryan Wanner Subject: [PATCH 11/15] ARM: dts: microchip: add sama7d65 SoC DT Date: Tue, 19 Nov 2024 09:40:17 -0700 Message-ID: <1006a1e4464ef7c46b33ad44bf71b3143283ee6e.1732030972.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241119_084123_249888_84C058AE X-CRM114-Status: GOOD ( 12.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ryan Wanner Add Device Tree for sama7d65 SoC. Signed-off-by: Ryan Wanner Co-developed-by: Romain Sioen Signed-off-by: Romain Sioen Co-developed-by: Varshini Rajendran Signed-off-by: Varshini Rajendran Signed-off-by: Dharma Balasubiramani --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 155 ++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi new file mode 100644 index 000000000000..2573d488bb81 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner + * + */ + +#include +#include +#include +#include +#include + +/ { + model = "Microchip SAMA7D65 family SoC"; + compatible = "microchip,sama7d65"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + vddout25: fixed-regulator-vddout25 { + compatible = "regulator-fixed"; + + regulator-name = "VDDOUT25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pioA: pinctrl@e0014000 { + compatible = "microchip,sama7d65-pinctrl"; + reg = <0xe0014000 0x800>; + interrupts = , + , + , + , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc: clock-controller@e0018000 { + compatible = "microchip,sama7d65-pmc", "syscon"; + reg = <0xe0018000 0x200>; + interrupts = ; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + clk32k: clock-controller@e001d500 { + compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; + reg = <0xe001d500 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + sdmmc1: mmc@e1208000 { + compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1208000 0x400>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 76>; + assigned-clock-rates = <200000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1800000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "pclk", "gclk"; + }; + + pit64b1: timer@e1804000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1804000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "pclk", "gclk"; + }; + + flx6: flexcom@e2020000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2020000 0x800>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "usart"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>; + }; + }; +};