Message ID | 11-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Update SMMUv3 to the modern iommu API (part 2/3) | expand |
On Tue, Mar 5, 2024 at 7:44 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > Half the code was living in arm_smmu_domain_finalise_s1(), just move it > here and take the values directly from the pgtbl_ops instead of storing > copies. > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 ++++++++------------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- > 2 files changed, 18 insertions(+), 32 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 50d17e3ce0a956..dfdd48cf217c4e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1301,15 +1301,25 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, > struct arm_smmu_domain *smmu_domain) > { > struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; > + const struct io_pgtable_cfg *pgtbl_cfg = > + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; > + typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = > + &pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > memset(target, 0, sizeof(*target)); > > target->data[0] = cpu_to_le64( > - cd->tcr | > + FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | > + FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | > + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | > + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | > + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | > + CTXDESC_CD_0_TCR_EPD1 | > #ifdef __BIG_ENDIAN > CTXDESC_CD_0_ENDI | > #endif > CTXDESC_CD_0_V | > + FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | I guess you're trying to keep these ordered by bit position, in which case EPD1 should go after ENDI. > CTXDESC_CD_0_AA64 | > (master->stall_enabled ? CTXDESC_CD_0_S : 0) | > CTXDESC_CD_0_R | > @@ -1317,9 +1327,9 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, > CTXDESC_CD_0_ASET | > FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) > ); > - > - target->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > - target->data[3] = cpu_to_le64(cd->mair); > + target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & > + CTXDESC_CD_1_TTB0_MASK); > + target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.mair); > } > > void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid) > @@ -2305,13 +2315,11 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) > } > > static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg) > + struct arm_smmu_domain *smmu_domain) > { > int ret; > u32 asid; > struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; > - typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > refcount_set(&cd->refs, 1); > > @@ -2319,31 +2327,13 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, > mutex_lock(&arm_smmu_asid_lock); > ret = xa_alloc(&arm_smmu_asid_xa, &asid, cd, > XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); > - if (ret) > - goto out_unlock; > - > cd->asid = (u16)asid; > - cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > - cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | > - FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | > - FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | > - FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | > - FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | > - FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | > - CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; > - cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; > - > - mutex_unlock(&arm_smmu_asid_lock); > - return 0; > - > -out_unlock: > mutex_unlock(&arm_smmu_asid_lock); > return ret; > } > > static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg) > + struct arm_smmu_domain *smmu_domain) > { > int vmid; > struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; > @@ -2367,8 +2357,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg pgtbl_cfg; > struct io_pgtable_ops *pgtbl_ops; > int (*finalise_stage_fn)(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg); > + struct arm_smmu_domain *smmu_domain); > > /* Restrict the stage to what we can actually support */ > if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) > @@ -2411,7 +2400,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, > smmu_domain->domain.geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; > smmu_domain->domain.geometry.force_aperture = true; > > - ret = finalise_stage_fn(smmu, smmu_domain, &pgtbl_cfg); > + ret = finalise_stage_fn(smmu, smmu_domain); > if (ret < 0) { > free_io_pgtable_ops(pgtbl_ops); > return ret; > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 8eabcccb9420ba..468cd33b80ac35 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -587,9 +587,6 @@ struct arm_smmu_strtab_l1_desc { > > struct arm_smmu_ctx_desc { > u16 asid; > - u64 ttbr; > - u64 tcr; > - u64 mair; > > refcount_t refs; > struct mm_struct *mm; > -- > 2.43.2 > Apart from the nit, Reviewed-by: Michael Shavit <mshavit@google.com>
On Fri, Mar 15, 2024 at 06:04:19PM +0800, Michael Shavit wrote: > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 50d17e3ce0a956..dfdd48cf217c4e 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -1301,15 +1301,25 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, > > struct arm_smmu_domain *smmu_domain) > > { > > struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; > > + const struct io_pgtable_cfg *pgtbl_cfg = > > + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; > > + typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = > > + &pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > > > memset(target, 0, sizeof(*target)); > > > > target->data[0] = cpu_to_le64( > > - cd->tcr | > > + FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | > > + FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | > > + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | > > + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | > > + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | > > + CTXDESC_CD_0_TCR_EPD1 | > > #ifdef __BIG_ENDIAN > > CTXDESC_CD_0_ENDI | > > #endif > > CTXDESC_CD_0_V | > > + FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | > > I guess you're trying to keep these ordered by bit position, in which > case EPD1 should go after ENDI. Right, I missed the #defines are not in bit order :\ Thanks, Jason
Hi Jason, On Mon, Mar 04, 2024 at 07:43:59PM -0400, Jason Gunthorpe wrote: > Half the code was living in arm_smmu_domain_finalise_s1(), just move it > here and take the values directly from the pgtbl_ops instead of storing > copies. > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 ++++++++------------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- > 2 files changed, 18 insertions(+), 32 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 50d17e3ce0a956..dfdd48cf217c4e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1301,15 +1301,25 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, > struct arm_smmu_domain *smmu_domain) > { > struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; > + const struct io_pgtable_cfg *pgtbl_cfg = > + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; > + typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = > + &pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > memset(target, 0, sizeof(*target)); > > target->data[0] = cpu_to_le64( > - cd->tcr | > + FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | > + FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | > + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | > + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | > + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | > + CTXDESC_CD_0_TCR_EPD1 | > #ifdef __BIG_ENDIAN > CTXDESC_CD_0_ENDI | > #endif > CTXDESC_CD_0_V | > + FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | > CTXDESC_CD_0_AA64 | > (master->stall_enabled ? CTXDESC_CD_0_S : 0) | > CTXDESC_CD_0_R | > @@ -1317,9 +1327,9 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, > CTXDESC_CD_0_ASET | > FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) > ); > - > - target->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > - target->data[3] = cpu_to_le64(cd->mair); > + target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & > + CTXDESC_CD_1_TTB0_MASK); > + target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.mair); > } > > void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid) > @@ -2305,13 +2315,11 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) > } > > static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg) > + struct arm_smmu_domain *smmu_domain) > { > int ret; > u32 asid; > struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; > - typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > refcount_set(&cd->refs, 1); > > @@ -2319,31 +2327,13 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, > mutex_lock(&arm_smmu_asid_lock); > ret = xa_alloc(&arm_smmu_asid_xa, &asid, cd, > XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); > - if (ret) > - goto out_unlock; > - > cd->asid = (u16)asid; > - cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > - cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | > - FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | > - FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | > - FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | > - FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | > - FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | > - CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; > - cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; > - > - mutex_unlock(&arm_smmu_asid_lock); > - return 0; > - > -out_unlock: > mutex_unlock(&arm_smmu_asid_lock); > return ret; > } > > static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg) > + struct arm_smmu_domain *smmu_domain) > { > int vmid; > struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; > @@ -2367,8 +2357,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg pgtbl_cfg; > struct io_pgtable_ops *pgtbl_ops; > int (*finalise_stage_fn)(struct arm_smmu_device *smmu, > - struct arm_smmu_domain *smmu_domain, > - struct io_pgtable_cfg *pgtbl_cfg); > + struct arm_smmu_domain *smmu_domain); > > /* Restrict the stage to what we can actually support */ > if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) > @@ -2411,7 +2400,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, > smmu_domain->domain.geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; > smmu_domain->domain.geometry.force_aperture = true; > > - ret = finalise_stage_fn(smmu, smmu_domain, &pgtbl_cfg); > + ret = finalise_stage_fn(smmu, smmu_domain); > if (ret < 0) { > free_io_pgtable_ops(pgtbl_ops); > return ret; > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 8eabcccb9420ba..468cd33b80ac35 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -587,9 +587,6 @@ struct arm_smmu_strtab_l1_desc { > > struct arm_smmu_ctx_desc { > u16 asid; > - u64 ttbr; > - u64 tcr; > - u64 mair; > > refcount_t refs; > struct mm_struct *mm; > -- > 2.43.2 > Reviewed-by: Mostafa Saleh <smostafa@google.com> Thanks, Mostafa
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 50d17e3ce0a956..dfdd48cf217c4e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1301,15 +1301,25 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_domain *smmu_domain) { struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; + const struct io_pgtable_cfg *pgtbl_cfg = + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; + typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = + &pgtbl_cfg->arm_lpae_s1_cfg.tcr; memset(target, 0, sizeof(*target)); target->data[0] = cpu_to_le64( - cd->tcr | + FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | + FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | + CTXDESC_CD_0_TCR_EPD1 | #ifdef __BIG_ENDIAN CTXDESC_CD_0_ENDI | #endif CTXDESC_CD_0_V | + FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | CTXDESC_CD_0_AA64 | (master->stall_enabled ? CTXDESC_CD_0_S : 0) | CTXDESC_CD_0_R | @@ -1317,9 +1327,9 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, CTXDESC_CD_0_ASET | FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) ); - - target->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); - target->data[3] = cpu_to_le64(cd->mair); + target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & + CTXDESC_CD_1_TTB0_MASK); + target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.mair); } void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid) @@ -2305,13 +2315,11 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) } static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain, - struct io_pgtable_cfg *pgtbl_cfg) + struct arm_smmu_domain *smmu_domain) { int ret; u32 asid; struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; - typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; refcount_set(&cd->refs, 1); @@ -2319,31 +2327,13 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, mutex_lock(&arm_smmu_asid_lock); ret = xa_alloc(&arm_smmu_asid_xa, &asid, cd, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - if (ret) - goto out_unlock; - cd->asid = (u16)asid; - cd->ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cd->tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | - FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | - FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | - FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | - FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | - FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | - CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; - cd->mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; - - mutex_unlock(&arm_smmu_asid_lock); - return 0; - -out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; } static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain, - struct io_pgtable_cfg *pgtbl_cfg) + struct arm_smmu_domain *smmu_domain) { int vmid; struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; @@ -2367,8 +2357,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain, - struct io_pgtable_cfg *pgtbl_cfg); + struct arm_smmu_domain *smmu_domain); /* Restrict the stage to what we can actually support */ if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) @@ -2411,7 +2400,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, smmu_domain->domain.geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; smmu_domain->domain.geometry.force_aperture = true; - ret = finalise_stage_fn(smmu, smmu_domain, &pgtbl_cfg); + ret = finalise_stage_fn(smmu, smmu_domain); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 8eabcccb9420ba..468cd33b80ac35 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -587,9 +587,6 @@ struct arm_smmu_strtab_l1_desc { struct arm_smmu_ctx_desc { u16 asid; - u64 ttbr; - u64 tcr; - u64 mair; refcount_t refs; struct mm_struct *mm;