From patchwork Mon Jan 19 16:21:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Clayton X-Patchwork-Id: 5659451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7640C9F4DC for ; Mon, 19 Jan 2015 16:24:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A3A2203B5 for ; Mon, 19 Jan 2015 16:24:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1B1520389 for ; Mon, 19 Jan 2015 16:24:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YDF5x-0007Dk-F8; Mon, 19 Jan 2015 16:22:29 +0000 Received: from atl4mhob13.myregisteredsite.com ([209.17.115.51]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YDF5s-0006sA-5i for linux-arm-kernel@lists.infradead.org; Mon, 19 Jan 2015 16:22:25 +0000 Received: from mailpod.hostingplatform.com ([10.30.71.208]) by atl4mhob13.myregisteredsite.com (8.14.4/8.14.4) with ESMTP id t0JGLvJ9003954 for ; Mon, 19 Jan 2015 11:21:57 -0500 Received: (qmail 29605 invoked by uid 0); 19 Jan 2015 16:21:57 -0000 X-TCPREMOTEIP: 68.185.59.186 X-Authenticated-UID: joshua.clayton@uniwest.com Received: from unknown (HELO jclayton-pc.localnet) (joshua.clayton@uniwest.com@68.185.59.186) by 0 with ESMTPA; 19 Jan 2015 16:21:57 -0000 From: Joshua Clayton To: linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH 2/5] irq: Allow interrupts to routed to NMI (or similar) Date: Mon, 19 Jan 2015 08:21:54 -0800 Message-ID: <11284577.ZthGdGvihU@jclayton-pc> Organization: UniWest User-Agent: KMail/4.14.1 (Linux/3.8.0-31-generic; KDE/4.14.1; x86_64; ; ) In-Reply-To: <1421166931-14134-3-git-send-email-daniel.thompson@linaro.org> References: <1421166931-14134-1-git-send-email-daniel.thompson@linaro.org> <1421166931-14134-3-git-send-email-daniel.thompson@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150119_082224_718228_4613567F X-CRM114-Status: GOOD ( 27.76 ) X-Spam-Score: -0.0 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , Jason Cooper , patches@linaro.org, Stephen Boyd , linux-kernel@vger.kernel.org, Daniel Drake , Dirk Behme , John Stultz , Tim Sander , Thomas Gleixner , Sumit Semwal , Dmitry Pervushin X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Daniel, feel free to ignore my comments. I know less about this than anybody :) I am especially unfamiliar with NMI, but I will risk exposing my ignorance On Tuesday, January 13, 2015 04:35:28 PM Daniel Thompson wrote: > Some combinations of architectures and interrupt controllers make it > possible for abitrary interrupt signals to be selectively made immune to > masking by local_irq_disable(). For example, on ARM platforms, many > interrupt controllers allow interrupts to be routed to FIQ rather than IRQ. > > These features could be exploited to implement debug and tracing features > that can be implemented using NMI on x86 platforms (perf, hard lockup, > kgdb). > > This patch assumes that the management of the NMI handler itself will be > architecture specific (maybe notifier list like x86, hard coded like ARM, > or something else entirely). The generic layer can still manage the irq > as normal (affinity, enable/disable, free) but is not responsible for > dispatching. > > Signed-off-by: Daniel Thompson > --- > include/linux/interrupt.h | 20 ++++++++++++++++++++ > include/linux/irq.h | 2 ++ > kernel/irq/manage.c | 29 +++++++++++++++++++++++++++-- > 3 files changed, 49 insertions(+), 2 deletions(-) > > diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h > index d9b05b5bf8c7..b95dc28f4cc3 100644 > --- a/include/linux/interrupt.h > +++ b/include/linux/interrupt.h > @@ -57,6 +57,9 @@ > * IRQF_NO_THREAD - Interrupt cannot be threaded > * IRQF_EARLY_RESUME - Resume IRQ early during syscore instead of at device > * resume time. > + * __IRQF_NMI - Route the interrupt to an NMI or some similar signal that > is not + * masked by local_irq_disable(). Used internally by + > * request_nmi_irq(). > */ > #define IRQF_DISABLED 0x00000020 > #define IRQF_SHARED 0x00000080 > @@ -70,6 +73,7 @@ > #define IRQF_FORCE_RESUME 0x00008000 > #define IRQF_NO_THREAD 0x00010000 > #define IRQF_EARLY_RESUME 0x00020000 > +#define __IRQF_NMI 0x00040000 > > #define IRQF_TIMER (__IRQF_TIMER | IRQF_NO_SUSPEND | IRQF_NO_THREAD) > > @@ -139,6 +143,22 @@ extern int __must_check > request_percpu_irq(unsigned int irq, irq_handler_t handler, > const char *devname, void __percpu *percpu_dev_id); > > +static inline int __must_check request_nmi_irq(unsigned int irq, > + unsigned long flags, > + const char *name, void *dev_id) Why not pass your handler in here, instead of adding explicitly it to the default FIQ handler? request_nmi_irq need not exist at all. Your __IRQF_NMI flag is sufficient with request_irq. > +{ > + /* > + * no_action unconditionally returns IRQ_NONE which is exactly > + * what we need. The handler might be expected to be unreachable > + * but some controllers may spuriously ack the NMI from the IRQ > + * handling code. When this happens it occurs very rarely, thus > + * by returning IRQ_NONE we can rely on the spurious interrupt > + * logic to do the right thing. > + */ > + return request_irq(irq, no_action, flags | IRQF_NO_THREAD | __IRQF_NMI, > + name, dev_id); no_action here looks kind of evil to me. I'd prefer to see the nonsecure irq handler check for __IRQF_NMI and call no_action. if (chip->irq_eoi) > +} > + > extern void free_irq(unsigned int, void *); > extern void free_percpu_irq(unsigned int, void __percpu *); > > diff --git a/include/linux/irq.h b/include/linux/irq.h > index d09ec7a1243e..695eb37f04ae 100644 > --- a/include/linux/irq.h > +++ b/include/linux/irq.h > @@ -307,6 +307,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct > irq_data *d) * @irq_eoi: end of interrupt > * @irq_set_affinity: set the CPU affinity on SMP machines > * @irq_retrigger: resend an IRQ to the CPU > + * @irq_set_nmi_routing:set whether interrupt can act like NMI > * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ > * @irq_set_wake: enable/disable power-management wake-on of an IRQ > * @irq_bus_lock: function to lock access to slow bus (i2c) chips > @@ -341,6 +342,7 @@ struct irq_chip { > > int (*irq_set_affinity)(struct irq_data *data, const struct cpumask > *dest, bool force); int (*irq_retrigger)(struct irq_data *data); > + int (*irq_set_nmi_routing)(struct irq_data *data, unsigned int nmi); > int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); > int (*irq_set_wake)(struct irq_data *data, unsigned int on); > > diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c > index 80692373abd6..8e669051759d 100644 > --- a/kernel/irq/manage.c > +++ b/kernel/irq/manage.c > @@ -571,6 +571,17 @@ int can_request_irq(unsigned int irq, unsigned long > irqflags) return canrequest; > } > > +int __irq_set_nmi_routing(struct irq_desc *desc, unsigned int irq, > + unsigned int nmi) > +{ > + struct irq_chip *chip = desc->irq_data.chip; > + > + if (!chip || !chip->irq_set_nmi_routing) > + return -EINVAL; > + > + return chip->irq_set_nmi_routing(&desc->irq_data, nmi); > +} > + > int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, > unsigned long flags) > { > @@ -1058,11 +1069,12 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, > struct irqaction *new) * the same type (level, edge, polarity). So both > flag > * fields must have IRQF_SHARED set and the bits which > * set the trigger type must match. Also all must > - * agree on ONESHOT. > + * agree on ONESHOT and NMI > */ > if (!((old->flags & new->flags) & IRQF_SHARED) || > ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) || > - ((old->flags ^ new->flags) & IRQF_ONESHOT)) > + ((old->flags ^ new->flags) & IRQF_ONESHOT) || > + ((old->flags ^ new->flags) & __IRQF_NMI)) > goto mismatch; > > /* All handlers must agree on per-cpuness */ > @@ -1153,6 +1165,19 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, > struct irqaction *new) > > init_waitqueue_head(&desc->wait_for_threads); > > + if (new->flags & __IRQF_NMI) { > + ret = __irq_set_nmi_routing(desc, irq, true); > + if (ret != 1) > + goto out_mask; > + } else { > + ret = __irq_set_nmi_routing(desc, irq, false); > + if (ret == 1) { > + pr_err("Failed to disable NMI routing for irq %d\n", > + irq); > + goto out_mask; > + } > + } > + > /* Setup the type (level, edge polarity) if configured: */ > if (new->flags & IRQF_TRIGGER_MASK) { > ret = __irq_set_trigger(desc, irq, > -- > 1.9.3 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 6f1c7a5..f810cff 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -711,7 +711,10 @@ void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) chip->irq_ack(&desc->irq_data); trace_irq_handler_entry(irq, action); - res = action->handler(irq, dev_id); + if (action->flags & __IRQF_NMI) + res = no_action(irq, dev_id); + else + res = action->handler(irq, dev_id); trace_irq_handler_exit(irq, action, res);