| Message ID | 113f1cecf1d83c6b96fd23ab9d7a73d1923e0d21.1442310569.git.shengjiu.wang@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote: > As spdif driver will register SPDIF clock to regmap, regmap will do > clk_prepare in init function, so SPDIF clock is prepared in probe, then its > root clock (pll clock) is prepared also, which cause the arm can't enter > low power mode. Can you help me understand why ARM cannot enter low power mode when pll clock is prepared? Shawn > Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock. > Its root clock is ipg clock, and register it to regmap, then the issue cam > be fixed. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> > --- > drivers/clk/imx/clk-imx6q.c | 4 +++- > drivers/clk/imx/clk-imx6sl.c | 4 +++- > drivers/clk/imx/clk-imx6sx.c | 1 + > include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- > include/dt-bindings/clock/imx6sl-clock.h | 3 ++- > include/dt-bindings/clock/imx6sx-clock.h | 3 ++- > 6 files changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c > index b2c1c04..e6b5944 100644 > --- a/drivers/clk/imx/clk-imx6q.c > +++ b/drivers/clk/imx/clk-imx6q.c > @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1; > static unsigned int share_count_ssi2; > static unsigned int share_count_ssi3; > static unsigned int share_count_mipi_core_cfg; > +static unsigned int share_count_spdif; > > static inline int clk_on_imx6q(void) > { > @@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); > clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); > clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > - clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); > + clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); > + clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); > clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c > index a0d4cf2..a73cedd 100644 > --- a/drivers/clk/imx/clk-imx6sl.c > +++ b/drivers/clk/imx/clk-imx6sl.c > @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = { > static unsigned int share_count_ssi1; > static unsigned int share_count_ssi2; > static unsigned int share_count_ssi3; > +static unsigned int share_count_spdif; > > static struct clk *clks[IMX6SL_CLK_END]; > static struct clk_onecell_data clk_data; > @@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) > clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); > clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); > clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > - clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); > + clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); > + clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); > clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c > index 5b95c2c..f2bc511 100644 > --- a/drivers/clk/imx/clk-imx6sx.c > +++ b/drivers/clk/imx/clk-imx6sx.c > @@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) > clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); > clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); > + clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); > clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h > index 8de173f..77985cc 100644 > --- a/include/dt-bindings/clock/imx6qdl-clock.h > +++ b/include/dt-bindings/clock/imx6qdl-clock.h > @@ -254,6 +254,7 @@ > #define IMX6QDL_CLK_CAAM_MEM 241 > #define IMX6QDL_CLK_CAAM_ACLK 242 > #define IMX6QDL_CLK_CAAM_IPG 243 > -#define IMX6QDL_CLK_END 244 > +#define IMX6QDL_CLK_SPDIF_GCLK 244 > +#define IMX6QDL_CLK_END 245 > > #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ > diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h > index 9ce4e42..e14573e 100644 > --- a/include/dt-bindings/clock/imx6sl-clock.h > +++ b/include/dt-bindings/clock/imx6sl-clock.h > @@ -174,6 +174,7 @@ > #define IMX6SL_CLK_SSI1_IPG 161 > #define IMX6SL_CLK_SSI2_IPG 162 > #define IMX6SL_CLK_SSI3_IPG 163 > -#define IMX6SL_CLK_END 164 > +#define IMX6SL_CLK_SPDIF_GCLK 164 > +#define IMX6SL_CLK_END 165 > > #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ > diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h > index 9957091..36f0324 100644 > --- a/include/dt-bindings/clock/imx6sx-clock.h > +++ b/include/dt-bindings/clock/imx6sx-clock.h > @@ -274,6 +274,7 @@ > #define IMX6SX_PLL5_BYPASS 261 > #define IMX6SX_PLL6_BYPASS 262 > #define IMX6SX_PLL7_BYPASS 263 > -#define IMX6SX_CLK_CLK_END 264 > +#define IMX6SX_CLK_SPDIF_GCLK 264 > +#define IMX6SX_CLK_CLK_END 265 > > #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ > -- > 1.9.1 >
On Wed, Sep 23, 2015 at 08:33:41AM -0700, Shawn Guo wrote: > On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote: > > As spdif driver will register SPDIF clock to regmap, regmap will do > > clk_prepare in init function, so SPDIF clock is prepared in probe, then its > > root clock (pll clock) is prepared also, which cause the arm can't enter > > low power mode. > > Can you help me understand why ARM cannot enter low power mode when pll > clock is prepared? > > Shawn Hi Shawn In i.mx clock framework, when pll clk is prepared, it will be powerup. when enterring low power idle mode, the powerdown bit is checked, when pll is not powerdown state, chip will not enter low power idle mode. best regards wang shengjiu > > > Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock. > > Its root clock is ipg clock, and register it to regmap, then the issue cam > > be fixed. > > > > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> > > --- > > drivers/clk/imx/clk-imx6q.c | 4 +++- > > drivers/clk/imx/clk-imx6sl.c | 4 +++- > > drivers/clk/imx/clk-imx6sx.c | 1 + > > include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- > > include/dt-bindings/clock/imx6sl-clock.h | 3 ++- > > include/dt-bindings/clock/imx6sx-clock.h | 3 ++- > > 6 files changed, 13 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c > > index b2c1c04..e6b5944 100644 > > --- a/drivers/clk/imx/clk-imx6q.c > > +++ b/drivers/clk/imx/clk-imx6q.c > > @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1; > > static unsigned int share_count_ssi2; > > static unsigned int share_count_ssi3; > > static unsigned int share_count_mipi_core_cfg; > > +static unsigned int share_count_spdif; > > > > static inline int clk_on_imx6q(void) > > { > > @@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > > clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); > > clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); > > clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > > - clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); > > + clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); > > + clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); > > clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > > clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > > clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > > diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c > > index a0d4cf2..a73cedd 100644 > > --- a/drivers/clk/imx/clk-imx6sl.c > > +++ b/drivers/clk/imx/clk-imx6sl.c > > @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = { > > static unsigned int share_count_ssi1; > > static unsigned int share_count_ssi2; > > static unsigned int share_count_ssi3; > > +static unsigned int share_count_spdif; > > > > static struct clk *clks[IMX6SL_CLK_END]; > > static struct clk_onecell_data clk_data; > > @@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) > > clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); > > clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); > > clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > > - clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); > > + clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); > > + clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); > > clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > > clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > > clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > > diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c > > index 5b95c2c..f2bc511 100644 > > --- a/drivers/clk/imx/clk-imx6sx.c > > +++ b/drivers/clk/imx/clk-imx6sx.c > > @@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) > > clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); > > clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); > > clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); > > + clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); > > clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); > > clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); > > clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); > > diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h > > index 8de173f..77985cc 100644 > > --- a/include/dt-bindings/clock/imx6qdl-clock.h > > +++ b/include/dt-bindings/clock/imx6qdl-clock.h > > @@ -254,6 +254,7 @@ > > #define IMX6QDL_CLK_CAAM_MEM 241 > > #define IMX6QDL_CLK_CAAM_ACLK 242 > > #define IMX6QDL_CLK_CAAM_IPG 243 > > -#define IMX6QDL_CLK_END 244 > > +#define IMX6QDL_CLK_SPDIF_GCLK 244 > > +#define IMX6QDL_CLK_END 245 > > > > #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ > > diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h > > index 9ce4e42..e14573e 100644 > > --- a/include/dt-bindings/clock/imx6sl-clock.h > > +++ b/include/dt-bindings/clock/imx6sl-clock.h > > @@ -174,6 +174,7 @@ > > #define IMX6SL_CLK_SSI1_IPG 161 > > #define IMX6SL_CLK_SSI2_IPG 162 > > #define IMX6SL_CLK_SSI3_IPG 163 > > -#define IMX6SL_CLK_END 164 > > +#define IMX6SL_CLK_SPDIF_GCLK 164 > > +#define IMX6SL_CLK_END 165 > > > > #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ > > diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h > > index 9957091..36f0324 100644 > > --- a/include/dt-bindings/clock/imx6sx-clock.h > > +++ b/include/dt-bindings/clock/imx6sx-clock.h > > @@ -274,6 +274,7 @@ > > #define IMX6SX_PLL5_BYPASS 261 > > #define IMX6SX_PLL6_BYPASS 262 > > #define IMX6SX_PLL7_BYPASS 263 > > -#define IMX6SX_CLK_CLK_END 264 > > +#define IMX6SX_CLK_SPDIF_GCLK 264 > > +#define IMX6SX_CLK_CLK_END 265 > > > > #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ > > -- > > 1.9.1 > >
On Thu, Sep 24, 2015 at 01:43:24PM +0800, Shengjiu Wang wrote: > On Wed, Sep 23, 2015 at 08:33:41AM -0700, Shawn Guo wrote: > > On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote: > > > As spdif driver will register SPDIF clock to regmap, regmap will do > > > clk_prepare in init function, so SPDIF clock is prepared in probe, then its > > > root clock (pll clock) is prepared also, which cause the arm can't enter > > > low power mode. > > > > Can you help me understand why ARM cannot enter low power mode when pll > > clock is prepared? > > > > Shawn > Hi Shawn > > In i.mx clock framework, when pll clk is prepared, it will be powerup. when > enterring low power idle mode, the powerdown bit is checked, when pll is not > powerdown state, chip will not enter low power idle mode. So this is not a SPDIF specific problem, and any device driver preparing its clock that is a child of pll clock will run into this problem, right? If so, we should purchase a more generic solution than such device specific one. Shawn
On Thu, Sep 24, 2015 at 04:57:37AM -0700, Shawn Guo wrote: > On Thu, Sep 24, 2015 at 01:43:24PM +0800, Shengjiu Wang wrote: > > On Wed, Sep 23, 2015 at 08:33:41AM -0700, Shawn Guo wrote: > > > On Tue, Sep 15, 2015 at 06:01:01PM +0800, Shengjiu Wang wrote: > > > > As spdif driver will register SPDIF clock to regmap, regmap will do > > > > clk_prepare in init function, so SPDIF clock is prepared in probe, then its > > > > root clock (pll clock) is prepared also, which cause the arm can't enter > > > > low power mode. > > > > > > Can you help me understand why ARM cannot enter low power mode when pll > > > clock is prepared? > > > > > > Shawn > > Hi Shawn > > > > In i.mx clock framework, when pll clk is prepared, it will be powerup. when > > enterring low power idle mode, the powerdown bit is checked, when pll is not > > powerdown state, chip will not enter low power idle mode. > > So this is not a SPDIF specific problem, and any device driver preparing > its clock that is a child of pll clock will run into this problem, > right? If so, we should purchase a more generic solution than such > device specific one. > > Shawn Hi shawn SPDIF_GCLK is also spdif's clock, it use a same enable bit with SPDIF_ROOT_CLK, We didn't separate them in clock tree before. I can't find a generic solution. But anyway if there is a solution or not, I think we'd better to separate them. best regards wang shengjiu
On Fri, Oct 09, 2015 at 05:15:30PM +0800, Shengjiu Wang wrote: > SPDIF_GCLK is also spdif's clock, it use a same enable bit with SPDIF_ROOT_CLK, > We didn't separate them in clock tree before. Is it the clock described as "Global clock" in Reference Manual, SPDIF chapter? If that's the case, you are just adding a missing SPDIF clock rather than fixing a low power mode issue, and I will be fine. But still you should reword the commit log to make it clear, that the patch is to correct a SPDIF clock setting issue, which is just discovered by low power mode support. Shawn
On Sat, Oct 10, 2015 at 09:11:55AM +0800, Shawn Guo wrote: > On Fri, Oct 09, 2015 at 05:15:30PM +0800, Shengjiu Wang wrote: > > SPDIF_GCLK is also spdif's clock, it use a same enable bit with SPDIF_ROOT_CLK, > > We didn't separate them in clock tree before. > > Is it the clock described as "Global clock" in Reference Manual, SPDIF Yes. > chapter? If that's the case, you are just adding a missing SPDIF clock > rather than fixing a low power mode issue, and I will be fine. But > still you should reword the commit log to make it clear, that the patch > is to correct a SPDIF clock setting issue, which is just discovered by > low power mode support. > Ok, I will refine the patch comments, and send it later. > Shawn
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b2c1c04..e6b5944 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -119,6 +119,7 @@ static unsigned int share_count_ssi1; static unsigned int share_count_ssi2; static unsigned int share_count_ssi3; static unsigned int share_count_mipi_core_cfg; +static unsigned int share_count_spdif; static inline int clk_on_imx6q(void) { @@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); - clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); + clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); + clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index a0d4cf2..a73cedd 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = { static unsigned int share_count_ssi1; static unsigned int share_count_ssi2; static unsigned int share_count_ssi3; +static unsigned int share_count_spdif; static struct clk *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; @@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); - clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); + clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); + clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 5b95c2c..f2bc511 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); + clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 8de173f..77985cc 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -254,6 +254,7 @@ #define IMX6QDL_CLK_CAAM_MEM 241 #define IMX6QDL_CLK_CAAM_ACLK 242 #define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_END 244 +#define IMX6QDL_CLK_SPDIF_GCLK 244 +#define IMX6QDL_CLK_END 245 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index 9ce4e42..e14573e 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -174,6 +174,7 @@ #define IMX6SL_CLK_SSI1_IPG 161 #define IMX6SL_CLK_SSI2_IPG 162 #define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_END 164 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index 9957091..36f0324 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -274,6 +274,7 @@ #define IMX6SX_PLL5_BYPASS 261 #define IMX6SX_PLL6_BYPASS 262 #define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_CLK_END 264 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_CLK_END 265 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
As spdif driver will register SPDIF clock to regmap, regmap will do clk_prepare in init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode. Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock. Its root clock is ipg clock, and register it to regmap, then the issue cam be fixed. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> --- drivers/clk/imx/clk-imx6q.c | 4 +++- drivers/clk/imx/clk-imx6sl.c | 4 +++- drivers/clk/imx/clk-imx6sx.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- 6 files changed, 13 insertions(+), 5 deletions(-)