| Message ID | 12d012d7ee372e43142bc4a56b0bbf3cb9c51c34.1703066422.git.michal.simek@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: xilinx: Add missing firmware child nodes | expand |
On 20/12/2023 11:00, Michal Simek wrote: > + gpio: > + $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# > + description: The gpio node describes connect to PS_MODE pins via firmware > + interface. > + type: object > + > + pcap: > + $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml > + description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to > + configure the Programmable Logic (PL). The configuration uses the > + firmware interface. > + type: object > + > + pinctrl: > + $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# > + description: The pinctrl node provides access to pinconfig and pincontrol > + functionality available in firmware. > + type: object > + > + power-controller: > + $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml# This should be "power-controller" only if it is a power domain provider. Is it? Bot's report suggest it is not, therefore I suggested power-management. Also, please extend the example. The top-level example for complex devices should be complete. Apologies for not bringing it earlier. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index 98945220c33c..310c334e88a2 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -41,6 +41,37 @@ properties: "#power-domain-cells": const: 1 + gpio: + $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# + description: The gpio node describes connect to PS_MODE pins via firmware + interface. + type: object + + pcap: + $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml + description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to + configure the Programmable Logic (PL). The configuration uses the + firmware interface. + type: object + + pinctrl: + $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# + description: The pinctrl node provides access to pinconfig and pincontrol + functionality available in firmware. + type: object + + power-controller: + $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml# + description: The zynqmp-power node describes the power management + configurations. It will control remote suspend/shutdown interfaces. + type: object + + reset-controller: + $ref: /schemas/reset/xlnx,zynqmp-reset.yaml# + description: The reset-controller node describes connection to the reset + functionality via firmware interface. + type: object + versal-fpga: $ref: /schemas/fpga/xlnx,versal-fpga.yaml# description: Compatible of the FPGA device.
Firmware node has more than fpga, aes and clock child nodes but also power, reset, gpio, pinctrl and pcap which are not described yet. All of them have binding in separate files but there is missing connection to firmware node that's why describe it. Signed-off-by: Michal Simek <michal.simek@amd.com> --- Changes in v2: - Sort nodes by name - Rename zynqmp-power to power-controller - Keep only single patch for easier handling as done in v1 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)