From patchwork Thu Aug 23 21:03:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 1368931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id E50D53FC66 for ; Thu, 23 Aug 2012 21:01:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T4eUF-00052t-DX; Thu, 23 Aug 2012 20:58:43 +0000 Received: from bombadil.infradead.org ([2001:4830:2446:ff00:4687:fcff:fea6:5117]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T4eUC-00052U-GX for linux-arm-kernel@merlin.infradead.org; Thu, 23 Aug 2012 20:58:41 +0000 Received: from zose-mta15.web4all.fr ([176.31.217.11]) by bombadil.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T4eU8-0007oR-QM for linux-arm-kernel@lists.infradead.org; Thu, 23 Aug 2012 20:58:38 +0000 Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id D888D2D2D4; Thu, 23 Aug 2012 23:01:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GSaF-L7IWp8y; Thu, 23 Aug 2012 23:01:14 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store-12.w4a.fr [178.33.204.48]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 4EF9B2C373; Thu, 23 Aug 2012 23:01:14 +0200 (CEST) Date: Thu, 23 Aug 2012 23:03:57 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: Thierry Reding , linux-kernel@vger.kernel.org, Sascha Hauer , linux-arm-kernel@lists.infradead.org Message-ID: <1305545087.2775440.1345755837651.JavaMail.root@advansee.com> In-Reply-To: <20120823191108.GB8127@avionic-0098.mockup.avionic-design.de> Subject: [PATCH] pwm-imx: Fix config / enable / disable MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20120823_165837_168432_38D1D33F X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-input@vger.kernel.org, linux-fbdev@vger.kernel.org, Lars-Peter Clausen , Florian Tobias Schandinat , Dmitry Torokhov , Richard Purdie , Bryan Wu , linux-leds@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org imx_pwm_config() did not enable the PWM IP clock while accessing the registers. Hence, a call to pwm_config() had no effect before pwm_enable() had been called, which does not comply to the PWM API. Moreover, calling pwm_disable() then pwm_enable() must be a transparent operation. This fixes the first setting of brightness through sysfs that had no effect with leds-pwm. Cc: Thierry Reding Cc: Cc: Sascha Hauer Cc: Cc: Benoît Thébaudeau Signed-off-by: Benoît Thébaudeau --- .../drivers/pwm/pwm-imx.c | 55 +++++++++++++++----- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git linux-next-c94456b.orig/drivers/pwm/pwm-imx.c linux-next-c94456b/drivers/pwm/pwm-imx.c index 2a0b353..0519bf2 100644 --- linux-next-c94456b.orig/drivers/pwm/pwm-imx.c +++ linux-next-c94456b/drivers/pwm/pwm-imx.c @@ -55,6 +55,16 @@ static int imx_pwm_config(struct pwm_chip *chip, { struct imx_chip *imx = to_imx_chip(chip); + /* + * If the PWM is disabled, make sure to turn on the clock before + * accessing the registers. + */ + if (!imx->clk_enabled) { + int rc = clk_prepare_enable(imx->clk); + if (rc) + return rc; + } + if (!(cpu_is_mx1() || cpu_is_mx21())) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; @@ -85,8 +95,11 @@ static int imx_pwm_config(struct pwm_chip *chip, writel(period_cycles, imx->mmio_base + MX3_PWMPR); cr = MX3_PWMCR_PRESCALER(prescale) | - MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | - MX3_PWMCR_DBGEN | MX3_PWMCR_EN; + MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN; + + /* If the PWM is enabled, keep it so. */ + if (imx->clk_enabled) + cr |= MX3_PWMCR_EN; if (cpu_is_mx25()) cr |= MX3_PWMCR_CLKSRC_IPG; @@ -118,32 +131,50 @@ static int imx_pwm_config(struct pwm_chip *chip, BUG(); } + /* If the PWM is disabled, turn the clock off again to save power. */ + if (!imx->clk_enabled) + clk_disable_unprepare(imx->clk); + return 0; } static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct imx_chip *imx = to_imx_chip(chip); - int rc = 0; + int rc; - if (!imx->clk_enabled) { - rc = clk_prepare_enable(imx->clk); - if (!rc) - imx->clk_enabled = 1; + if (imx->clk_enabled) + return 0; + + rc = clk_prepare_enable(imx->clk); + if (rc) + return rc; + + if (!(cpu_is_mx1() || cpu_is_mx21())) { + u32 cr = readl(imx->mmio_base + MX3_PWMCR); + cr |= MX3_PWMCR_EN; + writel(cr, imx->mmio_base + MX3_PWMCR); } - return rc; + + imx->clk_enabled = 1; + return 0; } static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct imx_chip *imx = to_imx_chip(chip); - writel(0, imx->mmio_base + MX3_PWMCR); + if (!imx->clk_enabled) + return; - if (imx->clk_enabled) { - clk_disable_unprepare(imx->clk); - imx->clk_enabled = 0; + if (!(cpu_is_mx1() || cpu_is_mx21())) { + u32 cr = readl(imx->mmio_base + MX3_PWMCR); + cr &= ~MX3_PWMCR_EN; + writel(cr, imx->mmio_base + MX3_PWMCR); } + + clk_disable_unprepare(imx->clk); + imx->clk_enabled = 0; } static struct pwm_ops imx_pwm_ops = {