From patchwork Tue May 31 08:31:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mattias Wallin X-Patchwork-Id: 832592 Received: from canuck.infradead.org (canuck.infradead.org [134.117.69.58]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p4VDMPSM009099 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 31 May 2011 13:22:46 GMT Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QRKMA-0006n7-Pd; Tue, 31 May 2011 08:31:18 +0000 Received: from eu1sys200aog117.obsmtp.com ([207.126.144.143]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1QRKM7-0006mo-Ml for linux-arm-kernel@lists.infradead.org; Tue, 31 May 2011 08:31:17 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKTeSnTghLawhI4cym2qdLXSjLQEJrywYi@postini.com; Tue, 31 May 2011 08:31:15 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 78980EC; Tue, 31 May 2011 08:31:06 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3F7DF1B14; Tue, 31 May 2011 08:31:05 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id F099CA8074; Tue, 31 May 2011 10:31:00 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 31 May 2011 10:31:04 +0200 From: Mattias Wallin To: Thomas Gleixner , , Subject: [PATCH 2/3] clocksource: add DB8500 PRCMU Timer support Date: Tue, 31 May 2011 10:31:01 +0200 Message-ID: <1306830661-9546-1-git-send-email-mattias.wallin@stericsson.com> X-Mailer: git-send-email 1.7.5.1 MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110531_043116_104188_03CD1F1A X-CRM114-Status: GOOD ( 20.98 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.143 listed in list.dnswl.org] Cc: Lee Jones , Mattias Wallin X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 31 May 2011 13:22:46 +0000 (UTC) This patch adds the DB8500 PRCMU Timer driver as a clocksource and as sched_clock. Signed-off-by: Mattias Wallin Acked-by: Linus Walleij --- drivers/clocksource/Kconfig | 15 +++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/clksrc-db8500-prcmu.c | 89 +++++++++++++++++++++++++++++ include/linux/clksrc-db8500-prcmu.h | 17 ++++++ 4 files changed, 122 insertions(+), 0 deletions(-) create mode 100644 drivers/clocksource/clksrc-db8500-prcmu.c create mode 100644 include/linux/clksrc-db8500-prcmu.h diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 96c9219..d7ee415 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -3,3 +3,18 @@ config CLKSRC_I8253 config CLKSRC_MMIO bool + +config CLKSRC_DB8500_PRCMU + bool "Clocksource PRCMU Timer" + depends on MFD_DB8500_PRCMU + default y + help + Use the always on PRCMU Timer as clocksource + +config CLKSRC_DB8500_PRCMU_SCHED_CLOCK + bool "Clocksource PRCMU Timer sched_clock" + depends on (CLKSRC_DB8500_PRCMU && !NOMADIK_MTU_SCHED_CLOCK) + select HAVE_SCHED_CLOCK + default y + help + Use the always on PRCMU Timer as sched_clock diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index b995942..f2308ba 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o obj-$(CONFIG_CLKSRC_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o +obj-$(CONFIG_CLKSRC_DB8500_PRCMU) += clksrc-db8500-prcmu.o diff --git a/drivers/clocksource/clksrc-db8500-prcmu.c b/drivers/clocksource/clksrc-db8500-prcmu.c new file mode 100644 index 0000000..07a4d1a --- /dev/null +++ b/drivers/clocksource/clksrc-db8500-prcmu.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Wallin for ST-Ericsson + * sched_clock implementation is based on: + * plat-nomadik/timer.c Linus Walleij + * + * Clocksource DB8500 PRCMU Timer + * The PRCMU in the DB8500 chip has 5 timers which + * are available in an always-on power domain. + * Timer 4 is dedicated to our always-on clock source. + */ +#include +#include +#include +#include +#include +#include + +#define RATE_32K (32768) + +#define TIMER_MODE_CONTINOUS (0x1) +#define TIMER_DOWNCOUNT_VAL (0xffffffff) + +/* PRCMU Timer 4 */ +#define PRCMU_TIMER_4_REF (prcmu_base + 0x450) +#define PRCMU_TIMER_4_DOWNCOUNT (prcmu_base + 0x454) +#define PRCMU_TIMER_4_MODE (prcmu_base + 0x458) + +static __iomem void *prcmu_base; + +#define SCHED_CLOCK_MIN_WRAP (131072) /* 2^32 / 32768 */ + +static cycle_t clksrc_db8500_prcmu_read(struct clocksource *cs) +{ + u32 count, count2; + + do { + count = readl(PRCMU_TIMER_4_DOWNCOUNT); + count2 = readl(PRCMU_TIMER_4_DOWNCOUNT); + } while (count2 != count); + + /* Negate because the timer is a decrementing counter */ + return ~count; +} + +static struct clocksource clocksource_db8500_prcmu = { + .name = "clksrc-db8500-prcmu-timer4", + .rating = 300, + .read = clksrc_db8500_prcmu_read, + .shift = 10, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +#ifdef CONFIG_CS_DB8500_PRCMU_SCHED_CLOCK +static DEFINE_CLOCK_DATA(cd); + +static void notrace clksrc_db8500_prcmu_update_sched_clock(void) +{ + u32 cyc = clksrc_db8500_prcmu_read(&clocksource_db8500_prcmu); + update_sched_clock(&cd, cyc, (u32)~0); +} +#endif + +void __init clksrc_db8500_prcmu_init(void) +{ + prcmu_base = __io_address(U8500_PRCMU_BASE); + + /* + * The A9 sub system expects the timer to be configured as + * a continous looping timer. + * The PRCMU should configure it but if it for some reason + * don't we do it here. + */ + if (readl(PRCMU_TIMER_4_MODE) != TIMER_MODE_CONTINOUS) { + writel(TIMER_MODE_CONTINOUS, PRCMU_TIMER_4_MODE); + writel(TIMER_DOWNCOUNT_VAL, PRCMU_TIMER_4_REF); + } +#ifdef CONFIG_CS_DB8500_PRCMU_SCHED_CLOCK + init_sched_clock(&cd, clksrc_db8500_prcmu_update_sched_clock, + 32, RATE_32K); +#endif + clocksource_calc_mult_shift(&clocksource_db8500_prcmu, + RATE_32K, SCHED_CLOCK_MIN_WRAP); + clocksource_register(&clocksource_db8500_prcmu); +} + diff --git a/include/linux/clksrc-db8500-prcmu.h b/include/linux/clksrc-db8500-prcmu.h new file mode 100644 index 0000000..42b8587 --- /dev/null +++ b/include/linux/clksrc-db8500-prcmu.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Wallin + * + */ +#ifndef __CLKSRC_DB8500_PRCMU_H +#define __CLKSRC_DB8500_PRCMU_H + +#ifdef CONFIG_CLKSRC_DB8500_PRCMU +void __init clksrc_db8500_prcmu_init(void); +#else +void __init clksrc_db8500_prcmu_init(void) {} +#endif + +#endif