From patchwork Tue May 31 19:02:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Petr_=C5=A0tetiar?= X-Patchwork-Id: 833302 Received: from canuck.infradead.org (canuck.infradead.org [134.117.69.58]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4VJ8LdO026327 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 31 May 2011 19:08:44 GMT Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QRUF3-0002i7-Hz; Tue, 31 May 2011 19:04:37 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QRUE9-0002c8-7B for linux-arm-kernel@canuck.infradead.org; Tue, 31 May 2011 19:03:41 +0000 Received: from ibawizard.net ([82.208.49.253] helo=mengele.ibawizard.net) by casper.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QRUEN-0000GZ-3z for linux-arm-kernel@lists.infradead.org; Tue, 31 May 2011 19:03:56 +0000 Received: from ntbk.lan (localhost [127.0.0.1]) by mengele.ibawizard.net (Postfix) with ESMTP id 3714F1D3612F; Tue, 31 May 2011 21:03:03 +0200 (CEST) From: =?UTF-8?q?Petr=20=C5=A0tetiar?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] ARM: ep93xx: use more reliable CPLD watchdog for reset on ts72xx Date: Tue, 31 May 2011 21:02:58 +0200 Message-Id: <1306868578-3883-1-git-send-email-ynezz@true.cz> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110531_200355_338922_96F1C71B X-CRM114-Status: GOOD ( 15.14 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2-r929478 on casper.infradead.org summary: Content analysis details: (-1.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Hartley Sweeten , =?UTF-8?q?Petr=20=C5=A0tetiar?= , Ryan Mallon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 31 May 2011 19:08:44 +0000 (UTC) X-MIME-Autoconverted: from base64 to 8bit by demeter1.kernel.org id p4VJ8LdO026327 On all ep93xx based boards from Technologic Systems, there's CPLD watchdog available, so use this one to reset the board instead of the soft reset in CPU. I've seen some weird lockups with the soft reset on ep93xx in the past, while the reset via CPLD watchdog seems to be rock solid (tm) and works fine so far. Cc: Hartley Sweeten Cc: Ryan Mallon Signed-off-by: Petr Štetiar Acked-by: H Hartley Sweeten --- arch/arm/mach-ep93xx/include/mach/system.h | 18 +++++++++++++----- 1 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index 6d661fe..2969786 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h @@ -2,7 +2,10 @@ * arch/arm/mach-ep93xx/include/mach/system.h */ +#include + #include +#include static inline void arch_idle(void) { @@ -13,11 +16,16 @@ static inline void arch_reset(char mode, const char *cmd) { local_irq_disable(); - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + /* It's more reliable to use CPLD watchdog to perform the reset */ + if (board_is_ts7200() || board_is_ts7250() || board_is_ts7260() || + board_is_ts7300() || board_is_ts7400()) { + __raw_writeb(0x5, TS72XX_WDT_FEED_PHYS_BASE); + __raw_writeb(0x1, TS72XX_WDT_CONTROL_PHYS_BASE); + } else { + /* Set then clear the SWRST bit to initiate a software reset */ + ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + } while (1) ;