From patchwork Thu Jun 9 10:54:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 864042 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p59Av5W1031257 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 9 Jun 2011 10:57:27 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QUcuU-0000Fq-VR; Thu, 09 Jun 2011 10:56:23 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QUcuR-00058X-K8; Thu, 09 Jun 2011 10:56:19 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QUcsc-0004gp-Mv for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2011 10:54:33 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p59AsKlT012286 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 9 Jun 2011 05:54:22 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p59AsHUj018053; Thu, 9 Jun 2011 16:24:20 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Thu, 9 Jun 2011 16:24:18 +0530 Received: from linfarm476.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p59AsGJa017570; Thu, 9 Jun 2011 16:24:16 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id p59AsGOu028769; Thu, 9 Jun 2011 16:24:16 +0530 Received: (from a0131687@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id p59AsGZK028767; Thu, 9 Jun 2011 16:24:16 +0530 From: Rajendra Nayak To: Subject: [PATCH 8/8] OMAP: clock: Enable clockdomain only for optional clocks Date: Thu, 9 Jun 2011 16:24:13 +0530 Message-ID: <1307616853-28395-9-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1307616853-28395-8-git-send-email-rnayak@ti.com> References: <1307616853-28395-1-git-send-email-rnayak@ti.com> <1307616853-28395-2-git-send-email-rnayak@ti.com> <1307616853-28395-3-git-send-email-rnayak@ti.com> <1307616853-28395-4-git-send-email-rnayak@ti.com> <1307616853-28395-5-git-send-email-rnayak@ti.com> <1307616853-28395-6-git-send-email-rnayak@ti.com> <1307616853-28395-7-git-send-email-rnayak@ti.com> <1307616853-28395-8-git-send-email-rnayak@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110609_065427_137016_85D1327C X-CRM114-Status: GOOD ( 13.10 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.40 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, paul@pwsan.com, b-cousson@ti.com, Rajendra Nayak , santosh.shilimkar@ti.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 09 Jun 2011 10:57:27 +0000 (UTC) Optional clocks have a requirement to have the clockdomain force enabled (SW_WKUP) before the optional clock itself is enabled. Since optional clocks are currently handled directly by drivers using the clock framework, this needs to be handled at the clock framework. This sequence is already handled in the omap_hwmod framework for the essential/main clocks. Signed-off-by: Rajendra Nayak --- arch/arm/mach-omap2/clock.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2828d29..ff71ff7 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -286,6 +286,7 @@ void omap2_clk_disable(struct clk *clk) int omap2_clk_enable(struct clk *clk) { int ret; + int hwsup = 0; pr_debug("clock: %s: incrementing usecount\n", clk->name); @@ -304,6 +305,17 @@ int omap2_clk_enable(struct clk *clk) goto oce_err1; } } + /* + * TODO: This is needed here only as long as drivers use + * clock framework to enable optional clocks. For all the + * essential clocks, this sequence is handled in the + * omap_hwmod framework. + */ + /* Enable the clockdomain, if its an optional clock */ + if ((clk->flags & CLOCK_OPTCLK) && (clk->clkdm)) { + hwsup = clkdm_is_idle(clk->clkdm); + clkdm_wakeup(clk->clkdm); + } if (clk->ops && clk->ops->enable) { trace_clock_enable(clk->name, 1, smp_processor_id()); @@ -315,6 +327,9 @@ int omap2_clk_enable(struct clk *clk) } } + if ((clk->flags & CLOCK_OPTCLK) && (clk->clkdm) && hwsup) + clkdm_allow_idle(clk->clkdm); + return 0; oce_err2: