From patchwork Tue Jun 21 11:24:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 901162 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p5LBUKex026077 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 21 Jun 2011 11:30:41 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYz9Y-00027U-Sy; Tue, 21 Jun 2011 11:29:57 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QYz9Y-0003Ie-G7; Tue, 21 Jun 2011 11:29:56 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QYz8s-00038w-Cz for linux-arm-kernel@lists.infradead.org; Tue, 21 Jun 2011 11:29:20 +0000 Received: from epcpsbgm2.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0LN5003O917SSGV0@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 21 Jun 2011 20:28:56 +0900 (KST) X-AuditID: cbfee61b-b7b2dae000007af9-a7-4e00807853a3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id 37.B7.31481.870800E4; Tue, 21 Jun 2011 20:28:56 +0900 (KST) Received: from Hawshines.sisodomain.com ([107.108.83.161]) by mmp2.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LN500MT817XCL@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 21 Jun 2011 20:28:56 +0900 (KST) Date: Tue, 21 Jun 2011 16:54:23 +0530 From: Naveen Krishna Chatradhi Subject: [PATCH v2 3/3] ARM: EXYNOS4: Add EPLL clock operations In-reply-to: <1308655463-8787-1-git-send-email-ch.naveen@samsung.com> To: kgene.kim@samsung.com, jassisinghbrar@gmail.com, sbkim73@samsung.com, sw.youn@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Message-id: <1308655463-8787-4-git-send-email-ch.naveen@samsung.com> X-Mailer: git-send-email 1.7.2.3 References: <1308655463-8787-1-git-send-email-ch.naveen@samsung.com> X-Brightmail-Tracker: AAAAAA== X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110621_072914_802240_05FA9952 X-CRM114-Status: GOOD ( 21.54 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [203.254.224.34 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.0 RFC_ABUSE_POST Both abuse and postmaster missing on sender domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 21 Jun 2011 11:30:41 +0000 (UTC) S5PV210 and EXYNOS4 uses similar PLL(PLL46XX) for EPLL. So, The EPLL set rate function is duplicated. Note: Moved common code to plat-s5p, as commented by Kukjin Kim. Signed-off-by: Naveen Krishna Chatradhi --- arch/arm/mach-exynos4/clock.c | 1 + arch/arm/mach-s5pv210/clock.c | 78 +--------------------------------- arch/arm/plat-s5p/clock.c | 77 +++++++++++++++++++++++++++++++++ arch/arm/plat-s5p/include/plat/pll.h | 3 + 4 files changed, 82 insertions(+), 77 deletions(-) diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index feeb27e..7687087 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1294,6 +1294,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) __raw_readl(S5P_VPLL_CON1), pll_4650); clk_fout_apll.ops = &exynos4_fout_apll_ops; + clk_fout_epll.ops = &pll46xx_epll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ae72f87..dd77c2c 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -979,82 +979,6 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_spdif, }; -static u32 epll_div[][6] = { - { 48000000, 0, 48, 3, 3, 0 }, - { 96000000, 0, 48, 3, 2, 0 }, - { 144000000, 1, 72, 3, 2, 0 }, - { 192000000, 0, 48, 3, 1, 0 }, - { 288000000, 1, 72, 3, 1, 0 }, - { 32750000, 1, 65, 3, 4, 35127 }, - { 32768000, 1, 65, 3, 4, 35127 }, - { 45158400, 0, 45, 3, 3, 10355 }, - { 45000000, 0, 45, 3, 3, 10355 }, - { 45158000, 0, 45, 3, 3, 10355 }, - { 49125000, 0, 49, 3, 3, 9961 }, - { 49152000, 0, 49, 3, 3, 9961 }, - { 67737600, 1, 67, 3, 3, 48366 }, - { 67738000, 1, 67, 3, 3, 48366 }, - { 73800000, 1, 73, 3, 3, 47710 }, - { 73728000, 1, 73, 3, 3, 47710 }, - { 36000000, 1, 32, 3, 4, 0 }, - { 60000000, 1, 60, 3, 3, 0 }, - { 72000000, 1, 72, 3, 3, 0 }, - { 80000000, 1, 80, 3, 3, 0 }, - { 84000000, 0, 42, 3, 2, 0 }, - { 50000000, 0, 50, 3, 3, 0 }, -}; - -static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int epll_con, epll_con_k; - unsigned int i; - - /* Return if nothing changed */ - if (clk->rate == rate) - return 0; - - epll_con = __raw_readl(S5P_EPLL_CON); - epll_con_k = __raw_readl(S5P_EPLL_CON1); - - epll_con_k &= ~PLL46XX_KDIV_MASK; - epll_con &= ~(1 << 27 | - PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | - PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | - PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); - - for (i = 0; i < ARRAY_SIZE(epll_div); i++) { - if (epll_div[i][0] == rate) { - epll_con_k |= epll_div[i][5] << 0; - epll_con |= (epll_div[i][1] << 27 | - epll_div[i][2] << PLL46XX_MDIV_SHIFT | - epll_div[i][3] << PLL46XX_PDIV_SHIFT | - epll_div[i][4] << PLL46XX_SDIV_SHIFT); - break; - } - } - - if (i == ARRAY_SIZE(epll_div)) { - printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", - __func__); - return -EINVAL; - } - - __raw_writel(epll_con, S5P_EPLL_CON); - __raw_writel(epll_con_k, S5P_EPLL_CON1); - - printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", - clk->rate, rate); - - clk->rate = rate; - - return 0; -} - -static struct clk_ops s5pv210_epll_ops = { - .set_rate = s5pv210_epll_set_rate, - .get_rate = s5p_epll_get_rate, -}; - void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; @@ -1075,7 +999,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) /* Set functions for clk_fout_epll */ clk_fout_epll.enable = s5p_epll_enable; - clk_fout_epll.ops = &s5pv210_epll_ops; + clk_fout_epll.ops = &pll46xx_epll_ops; printk(KERN_DEBUG "%s: registering clocks\n", __func__); diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 02af235..2a4678d 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -203,6 +204,82 @@ struct clk_ops s5p_sclk_spdif_ops = { .get_rate = s5p_spdif_get_rate, }; +static u32 epll_div[][6] = { + { 48000000, 0, 48, 3, 3, 0 }, + { 96000000, 0, 48, 3, 2, 0 }, + { 144000000, 1, 72, 3, 2, 0 }, + { 192000000, 0, 48, 3, 1, 0 }, + { 288000000, 1, 72, 3, 1, 0 }, + { 32750000, 1, 65, 3, 4, 35127 }, + { 32768000, 1, 65, 3, 4, 35127 }, + { 45158400, 0, 45, 3, 3, 10355 }, + { 45000000, 0, 45, 3, 3, 10355 }, + { 45158000, 0, 45, 3, 3, 10355 }, + { 49125000, 0, 49, 3, 3, 9961 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 67737600, 1, 67, 3, 3, 48366 }, + { 67738000, 1, 67, 3, 3, 48366 }, + { 73800000, 1, 73, 3, 3, 47710 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 36000000, 1, 32, 3, 4, 0 }, + { 60000000, 1, 60, 3, 3, 0 }, + { 72000000, 1, 72, 3, 3, 0 }, + { 80000000, 1, 80, 3, 3, 0 }, + { 84000000, 0, 42, 3, 2, 0 }, + { 50000000, 0, 50, 3, 3, 0 }, +}; + +int pll46xx_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + epll_con_k = __raw_readl(S5P_EPLL_CON1); + + epll_con_k &= ~PLL46XX_KDIV_MASK; + epll_con &= ~(1 << 27 | + PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | + PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | + PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k |= epll_div[i][5] << 0; + epll_con |= (epll_div[i][1] << 27 | + epll_div[i][2] << PLL46XX_MDIV_SHIFT | + epll_div[i][3] << PLL46XX_PDIV_SHIFT | + epll_div[i][4] << PLL46XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + __raw_writel(epll_con_k, S5P_EPLL_CON1); + + printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", + clk->rate, rate); + + clk->rate = rate; + + return 0; +} + +struct clk_ops pll46xx_epll_ops = { + .set_rate = pll46xx_epll_set_rate, + .get_rate = s5p_epll_get_rate, +}; + static struct clk *s5p_clks[] __initdata = { &clk_ext_xtal_mux, &clk_48m, diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index bf28fad..911a20e 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -94,6 +94,9 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, return result; } +extern int pll46xx_epll_set_rate(struct clk *clk, unsigned long rate); +extern struct clk_ops pll46xx_epll_ops; + #define PLL90XX_MDIV_MASK (0xFF) #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7)