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Thu, 7 Jul 2011 07:38:46 +0100 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by rly08d.srv.mailcontrol.com (MailControl) id p676bw1D012363 for ; Thu, 7 Jul 2011 07:37:58 +0100 Received: from banasiexc01.ASIA.ROOT.PRI ([202.80.51.114]) by rly08d-eth0.srv.mailcontrol.com (envelope-sender ) (MIMEDefang) with ESMTP id p676bn6u012026 (TLS bits=128 verify=FAIL); Thu, 07 Jul 2011 07:37:58 +0100 (BST) Received: from SHAASIEXC02.ASIA.ROOT.PRI (10.125.12.85) by banasiexc01.ASIA.ROOT.PRI (10.190.12.21) with Microsoft SMTP Server (TLS) id 14.1.270.1; Thu, 7 Jul 2011 12:07:55 +0530 Received: from localhost.localdomain (10.125.4.148) by asimail.csr.com (10.125.12.88) with Microsoft SMTP Server (TLS) id 14.1.270.1; Thu, 7 Jul 2011 14:37:53 +0800 From: Barry Song To: , , , Subject: [PATCH v4 3/3] ARM: CSR: initializing L2 cache Date: Wed, 6 Jul 2011 23:36:56 -0700 Message-ID: <1310020616-27856-4-git-send-email-bs14@csr.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1310020616-27856-1-git-send-email-bs14@csr.com> References: <1310020616-27856-1-git-send-email-bs14@csr.com> MIME-Version: 1.0 X-Originating-IP: [10.125.4.148] X-Scanned-By: MailControl A-12-00-01 (www.mailcontrol.com) on 10.68.1.118 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110707_023848_438023_F5E0C9A2 X-CRM114-Status: GOOD ( 17.21 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [85.115.60.190 listed in list.dnswl.org] Cc: devicetree-discuss@lists.ozlabs.org, workgroup.linux@csr.com, grant.likely@secretlab.ca, Rongjun Ying , Barry Song , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 07 Jul 2011 06:39:27 +0000 (UTC) From: Rongjun Ying Signed-off-by: Rongjun Ying Signed-off-by: Barry Song --- arch/arm/mach-prima2/Makefile | 1 + arch/arm/mach-prima2/l2x0.c | 59 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-prima2/l2x0.c diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index f2fba66..7af7fc0 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -4,3 +4,4 @@ obj-y += clock.o obj-y += rstc.o obj-y += prima2.o obj-$(CONFIG_DEBUG_LL) += lluart.o +obj-$(CONFIG_CACHE_L2X0) += l2x0.o diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c new file mode 100644 index 0000000..9cda205 --- /dev/null +++ b/arch/arm/mach-prima2/l2x0.c @@ -0,0 +1,59 @@ +/* + * l2 cache initialization for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define L2X0_ADDR_FILTERING_START 0xC00 +#define L2X0_ADDR_FILTERING_END 0xC04 + +static struct of_device_id l2x_ids[] = { + { .compatible = "arm,pl310-cache" }, +}; + +static int __init sirfsoc_of_l2x_init(void) +{ + struct device_node *np; + void __iomem *sirfsoc_l2x_base; + + np = of_find_matching_node(NULL, l2x_ids); + if (!np) + panic("unable to find compatible l2x node in dtb\n"); + + sirfsoc_l2x_base = of_iomap(np, 0); + if (!sirfsoc_l2x_base) + panic("unable to map l2x cpu registers\n"); + + of_node_put(np); + + if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) { + /* + * set the physical memory windows L2 cache will cover + */ + writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024, + sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END); + writel_relaxed(PLAT_PHYS_OFFSET | 0x1, + sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START); + + writel_relaxed(0, + sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0, + sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL); + } + l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000, + 0x00000000); + + return 0; +} +early_initcall(sirfsoc_of_l2x_init);