From patchwork Tue Jul 12 10:13:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 967922 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6CACxuv023326 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 12 Jul 2011 10:13:20 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgZxQ-0000rl-1Y; Tue, 12 Jul 2011 10:12:48 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QgZxP-0002yV-Lo; Tue, 12 Jul 2011 10:12:47 +0000 Received: from ch1ehsobe001.messaging.microsoft.com ([216.32.181.181] helo=ch1outboundpool.messaging.microsoft.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgZxM-0002y9-Ad for linux-arm-kernel@lists.infradead.org; Tue, 12 Jul 2011 10:12:45 +0000 Received: from mail160-ch1-R.bigfish.com (216.32.181.173) by CH1EHSOBE013.bigfish.com (10.43.70.63) with Microsoft SMTP Server id 14.1.225.22; Tue, 12 Jul 2011 10:12:38 +0000 Received: from mail160-ch1 (localhost.localdomain [127.0.0.1]) by mail160-ch1-R.bigfish.com (Postfix) with ESMTP id C0A126F0306; Tue, 12 Jul 2011 10:12:38 +0000 (UTC) X-SpamScore: -3 X-BigFish: VS-3(zz3b49Kzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail160-ch1 (localhost.localdomain [127.0.0.1]) by mail160-ch1 (MessageSwitch) id 1310465558200573_9617; Tue, 12 Jul 2011 10:12:38 +0000 (UTC) Received: from CH1EHSMHS030.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.243]) by mail160-ch1.bigfish.com (Postfix) with ESMTP id 25B91708050; Tue, 12 Jul 2011 10:12:38 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS030.bigfish.com (10.43.70.30) with Microsoft SMTP Server (TLS) id 14.1.225.22; Tue, 12 Jul 2011 10:12:30 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Tue, 12 Jul 2011 05:12:23 -0500 Received: from x-VirtualBox.ap.freescale.net ([10.192.242.1]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p6CACJDe014520; Tue, 12 Jul 2011 05:12:20 -0500 (CDT) From: Richard Zhu To: Subject: [PATCH V3] mmc: Enable the ADMA2 on esdhc imx driver Date: Tue, 12 Jul 2011 18:13:29 +0800 Message-ID: <1310465609-4516-1-git-send-email-richard.zhu@linaro.org> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110712_061244_786391_889BF4CF X-CRM114-Status: GOOD ( 21.73 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.181 listed in list.dnswl.org] Cc: cjb@laptop.org, pma@sysgo.com, w.sang@pengutronix.de, eric.miao@linaro.org, Richard Zhu , kernel@pengutronix.de, avorontsov@ru.mvista.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 12 Jul 2011 10:13:20 +0000 (UTC) Eanble the ADMA2 mode on freescale esdhc imx driver, tested on MX25, MX51 and MX53. Only ADMA2 mode is enabled, MX25/35 can't support the ADMA2 mode. So this patch is only used to enable the ADMA2 for MX51/53 platforms. The ADMA2 mode supported or not can be distinguished by the bit20 of Capability Register(offset 0x40) and bit9-8 of HOST PROTOCOL Register(offset 0x28) in FSL eSDHC module. BTW:Here are the definition of the Bit9~8 DMAS of HOST PROTOCOL Reg(offset 0x28). The bit9 couldn't be set to 1 when the SOC can't support ADMA2. This bit is used to make a double check that the ADMA2 is supported or not in this patch, since the bit20 of Capability Reg is broken on SOCs. DMAS definitions: 00: No DMA or Simple DMA is selected 01: ADMA1 is selected 10: ADMA2 is selected 11: reserved Signed-off-by: Richard Zhu --- drivers/mmc/host/sdhci-esdhc-imx.c | 45 ++++++++++++++++++++++++++++++++++- 1 files changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index a19967d..46092c7 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,6 +31,14 @@ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +/* + * There is INT DMA ERR mis-match between eSDHC and STD SDHC SPEC + * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, + * but bit28 is used as the INT DMA ERR in fsl eSDHC design. + * Define this macro DMA error INT for fsl eSDHC + */ +#define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000 + #define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0) /* * The CMDTYPE of the CMD register (offset 0xE) should be set to @@ -62,6 +70,7 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = pltfm_host->priv; + u32 dma_mode; /* fake CARD_PRESENT flag on mx25/35 */ u32 val = readl(host->ioaddr + reg); @@ -80,6 +89,30 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= SDHCI_CARD_PRESENT; } + if (unlikely(reg == SDHCI_CAPABILITIES)) { + /* In FSL esdhc IC module, only bit20 is used to indicate the + * ADMA2 capability of esdhc, but this bit is messed up on some + * SOCs (e.x MX25, this bit is set, but it can't support the + * ADMA2 actually). So readout HOST_CONTROl register to make a + * double check that the ADMA2 is supported or not. + */ + dma_mode = readl(host->ioaddr + SDHCI_HOST_CONTROL) >> 5; + dma_mode &= SDHCI_CTRL_DMA_MASK; + + if ((val & SDHCI_CAN_DO_ADMA1) + && (dma_mode > SDHCI_CTRL_ADMA1)) { + val &= ~SDHCI_CAN_DO_ADMA1; + val |= SDHCI_CAN_DO_ADMA2; + } + } + + if (unlikely(reg == SDHCI_INT_STATUS)) { + if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { + val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; + val |= SDHCI_INT_ADMA_ERROR; + } + } + return val; } @@ -105,6 +138,13 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); } + if (unlikely((reg == SDHCI_INT_ENABLE) + || (reg == SDHCI_SIGNAL_ENABLE))) { + if (val & SDHCI_INT_ADMA_ERROR) { + val &= ~SDHCI_INT_ADMA_ERROR; + val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR; + } + } writel(val, host->ioaddr + reg); } @@ -322,9 +362,10 @@ static void esdhc_pltfm_exit(struct sdhci_host *host) } struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { - .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA + .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT + | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC + | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_BROKEN_CARD_DETECTION, - /* ADMA has issues. Might be fixable */ .ops = &sdhci_esdhc_ops, .init = esdhc_pltfm_init, .exit = esdhc_pltfm_exit,