From patchwork Tue Jul 12 22:36:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Poynor X-Patchwork-Id: 969492 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6CMavhL000534 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 12 Jul 2011 22:37:19 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QglZR-0002qn-SI; Tue, 12 Jul 2011 22:36:50 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QglZR-00062d-Gk; Tue, 12 Jul 2011 22:36:49 +0000 Received: from smtp-out.google.com ([74.125.121.67]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QglZP-00062I-AA for linux-arm-kernel@lists.infradead.org; Tue, 12 Jul 2011 22:36:48 +0000 Received: from hpaq7.eem.corp.google.com (hpaq7.eem.corp.google.com [172.25.149.7]) by smtp-out.google.com with ESMTP id p6CMajWS023840; Tue, 12 Jul 2011 15:36:45 -0700 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=google.com; s=beta; t=1310510205; bh=pWlnlsuad9Cy9MG9tptOHxMk3CE=; h=From:To:Cc:Subject:Date:Message-Id; b=Qv7G6NGZNDK/60X5Yc/mXUianyDZtP3DBtXoQWgG1voyh4Jo4+wM1PGwse2c+w00F UcN2xUrSQKEPBOW46siCA== DomainKey-Signature: a=rsa-sha1; s=beta; d=google.com; c=nofws; q=dns; h=from:to:cc:subject:date:message-id:x-mailer; b=gjmWH/cfRozIH9kG7X43nQRHtxojQeEjD0t7XM+raYpd23TNQUvzctihv0WYNprN1 iESjeDjI6cPDRzsh10TGw== Received: from conslugarocko.mtv.corp.google.com (conslugarocko.mtv.corp.google.com [172.18.102.26]) by hpaq7.eem.corp.google.com with ESMTP id p6CMahuc003439; Tue, 12 Jul 2011 15:36:44 -0700 Received: by conslugarocko.mtv.corp.google.com (Postfix, from userid 115684) id 28F8723432E; Tue, 12 Jul 2011 15:36:43 -0700 (PDT) From: Todd Poynor To: Nicolas Pitre Subject: [PATCH 2/4] ARM: orion: Check NULL return from irq_alloc_generic_chip Date: Tue, 12 Jul 2011 15:36:40 -0700 Message-Id: <1310510200-4417-1-git-send-email-toddpoynor@google.com> X-Mailer: git-send-email 1.7.3.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110712_183647_647831_8DF32F37 X-CRM114-Status: GOOD ( 12.27 ) X-Spam-Score: -1.7 (-) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-1.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.121.67 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.7 FRT_TODAY2 BODY: ReplaceTags: Today (2) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Todd Poynor , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 12 Jul 2011 22:37:19 +0000 (UTC) Signed-off-by: Todd Poynor --- arch/arm/plat-orion/gpio.c | 7 +++++++ arch/arm/plat-orion/irq.c | 7 +++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 5b4fffa..ddc20d3 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -419,6 +419,13 @@ void __init orion_gpio_init(int gpio_base, int ngpio, gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base, ochip->base, handle_level_irq); + + if (!gc) { + pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n", + __func__, secondary_irq_base); + return; + } + gc->private = ochip; ct = gc->chip_types; diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 2d5b9c1..41e6e82 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -26,6 +26,13 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, handle_level_irq); + + if (!gc) { + pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n", + __func__, irq_start); + return; + } + ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit;