From patchwork Tue Jul 19 03:34:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 988122 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6J3Mu5X014358 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 19 Jul 2011 03:23:17 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qj0tS-00068m-Lo; Tue, 19 Jul 2011 03:22:46 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qj0tS-0003sC-9W; Tue, 19 Jul 2011 03:22:46 +0000 Received: from mail-iw0-f177.google.com ([209.85.214.177]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qj0tN-0003rs-V9 for linux-arm-kernel@lists.infradead.org; Tue, 19 Jul 2011 03:22:43 +0000 Received: by iwn35 with SMTP id 35so4168970iwn.36 for ; Mon, 18 Jul 2011 20:22:37 -0700 (PDT) Received: by 10.42.169.199 with SMTP id c7mr7432200icz.407.1311045757043; Mon, 18 Jul 2011 20:22:37 -0700 (PDT) Received: from localhost.localdomain ([114.216.156.94]) by mx.google.com with ESMTPS id d5sm3303410ibi.62.2011.07.18.20.22.01 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jul 2011 20:22:36 -0700 (PDT) From: Shawn Guo To: linux-kernel@vger.kernel.org Subject: [PATCH] gpio/mxc/mxs: fix build error introduced by the reanming of irq_gc_ack() Date: Tue, 19 Jul 2011 11:34:04 +0800 Message-Id: <1311046444-25423-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110718_232242_159988_4ED0C0B1 X-CRM114-Status: GOOD ( 11.62 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] Cc: Grant Likely , Shawn Guo , linux-arm-kernel@lists.infradead.org, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 19 Jul 2011 03:23:17 +0000 (UTC) The following commit renames irq_gc_ack() to irq_gc_ack_set_bit(), and makes gpio-mxc and gpio-mxs fail to build. 659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5 genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd) Signed-off-by: Shawn Guo --- The build error is being seen on linux-next. drivers/gpio/gpio-mxc.c | 2 +- drivers/gpio/gpio-mxs.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 89fda58..4a46fbe 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -297,7 +297,7 @@ static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) gc->private = port; ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack, + ct->chip.irq_ack = irq_gc_ack_set_bit, ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = gpio_set_irq_type; diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index d8cafba..88f8506 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -156,7 +156,7 @@ static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port) gc->private = port; ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack, + ct->chip.irq_ack = irq_gc_ack_set_bit, ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = mxs_gpio_set_irq_type;