From patchwork Fri Aug 5 02:54:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song X-Patchwork-Id: 1037242 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p752uJgO032398 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 5 Aug 2011 02:56:41 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QpAZv-0005VN-N4; Fri, 05 Aug 2011 02:56:04 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QpAZs-0007u2-Si; Fri, 05 Aug 2011 02:56:00 +0000 Received: from cluster-g.mailcontrol.com ([208.87.233.190]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QpAZp-0007tj-5E for linux-arm-kernel@lists.infradead.org; Fri, 05 Aug 2011 02:55:58 +0000 Received: from rly29g.srv.mailcontrol.com (localhost.localdomain [127.0.0.1]) by rly29g.srv.mailcontrol.com (MailControl) with ESMTP id p752tnlq014107 for ; Fri, 5 Aug 2011 03:55:51 +0100 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by rly29g.srv.mailcontrol.com (MailControl) id p752tP7r009288 for ; Fri, 5 Aug 2011 03:55:25 +0100 Received: from banasiexc01.ASIA.ROOT.PRI ([202.80.51.114]) by rly29g-eth0.srv.mailcontrol.com (envelope-sender ) (MIMEDefang) with ESMTP id p752tLVt009006 (TLS bits=128 verify=FAIL); Fri, 05 Aug 2011 03:55:25 +0100 (BST) Received: from SHAASIEXC01.ASIA.ROOT.PRI (10.125.12.84) by banasiexc01.ASIA.ROOT.PRI (10.190.12.21) with Microsoft SMTP Server (TLS) id 14.1.270.1; Fri, 5 Aug 2011 08:25:20 +0530 Received: from localhost.localdomain (10.125.36.59) by asimail.csr.com (10.125.12.88) with Microsoft SMTP Server (TLS) id 14.1.270.1; Fri, 5 Aug 2011 10:55:18 +0800 From: Barry Song To: , Subject: [RFC PATCH 1/2] ARM: CSR: add rtc i/o bridge interface for SiRFprimaII Date: Thu, 4 Aug 2011 19:54:47 -0700 Message-ID: <1312512888-25070-2-git-send-email-bs14@csr.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1312512888-25070-1-git-send-email-bs14@csr.com> References: <1312512888-25070-1-git-send-email-bs14@csr.com> MIME-Version: 1.0 X-Originating-IP: [10.125.36.59] X-Scanned-By: MailControl A-12-01-02 (www.mailcontrol.com) on 10.71.1.139 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110804_225557_419699_13BBC784 X-CRM114-Status: GOOD ( 19.37 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [208.87.233.190 listed in list.dnswl.org] Cc: Barry Song , workgroup.linux@csr.com, linux-arm-kernel@lists.infradead.org, Zhiwu Song X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 05 Aug 2011 02:56:41 +0000 (UTC) From: Zhiwu Song The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song Signed-off-by: Barry Song --- arch/arm/mach-prima2/Makefile | 1 + arch/arm/mach-prima2/rtciobrg.c | 118 ++++++++++++++++++++++++++++++++++ include/linux/rtc/sirfsoc_rtciobrg.h | 18 +++++ 3 files changed, 137 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-prima2/rtciobrg.c create mode 100644 include/linux/rtc/sirfsoc_rtciobrg.h diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 7af7fc0..f49d70b 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -3,5 +3,6 @@ obj-y += irq.o obj-y += clock.o obj-y += rstc.o obj-y += prima2.o +obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c new file mode 100644 index 0000000..0dc29f8 --- /dev/null +++ b/arch/arm/mach-prima2/rtciobrg.c @@ -0,0 +1,118 @@ +/* + * RTC I/O Bridge interfaces for CSR SiRFprimaII + * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include + +#define SIRFSOC_CPUIOBRG_CTRL 0x00 +#define SIRFSOC_CPUIOBRG_WRBE 0x04 +#define SIRFSOC_CPUIOBRG_ADDR 0x08 +#define SIRFSOC_CPUIOBRG_DATA 0x0c + +void __iomem *sirfsoc_rtciobrg_base; +static DEFINE_SPINLOCK(rtciobrg_lock); + +void sirfsoc_rtc_iobrg_wait_sync(void) +{ + while (readl(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) + cpu_relax(); +} + +void sirfsoc_rtc_iobrg_besyncing(void) +{ + unsigned long flags; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + sirfsoc_rtc_iobrg_wait_sync(); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); +} +EXPORT_SYMBOL(sirfsoc_rtc_iobrg_besyncing); + +u32 __sirfsoc_rtc_iobrg_readl(u32 addr) +{ + unsigned long val; + + sirfsoc_rtc_iobrg_wait_sync(); + + writel(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); + writel(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); + writel(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); + + sirfsoc_rtc_iobrg_wait_sync(); + + val = readl(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); + + return val; +} + +u32 sirfsoc_rtc_iobrg_readl(u32 addr) +{ + unsigned long flags, val; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + val = __sirfsoc_rtc_iobrg_readl(addr); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); + + return val; +} +EXPORT_SYMBOL(sirfsoc_rtc_iobrg_readl); + +void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) +{ + sirfsoc_rtc_iobrg_wait_sync(); + + writel(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); + writel(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); + + writel(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); +} + +void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) +{ + unsigned long flags = 0; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + sirfsoc_rtc_iobrg_pre_writel(val, addr); + + writel(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); + + sirfsoc_rtc_iobrg_wait_sync(); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); +} +EXPORT_SYMBOL(sirfsoc_rtc_iobrg_writel); + +static struct of_device_id rtciobrg_ids[] = { + { .compatible = "sirf,prima2-rtciobg" }, +}; + +static int __init sirfsoc_of_rtciobrg_map(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, rtciobrg_ids); + if (!np) + panic("unable to find compatible rtc iobrg node in dtb\n"); + sirfsoc_rtciobrg_base = of_iomap(np, 0); + if (!sirfsoc_rtciobrg_base) + panic("unable to map rtc iobrg registers\n"); + + of_node_put(np); + + return 0; +} +early_initcall(sirfsoc_of_rtciobrg_map); diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h new file mode 100644 index 0000000..2c92e1c --- /dev/null +++ b/include/linux/rtc/sirfsoc_rtciobrg.h @@ -0,0 +1,18 @@ +/* + * RTC I/O Bridge interfaces for CSR SiRFprimaII + * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ +#ifndef _SIRFSOC_RTC_IOBRG_H_ +#define _SIRFSOC_RTC_IOBRG_H_ + +extern void sirfsoc_rtc_iobrg_besyncing(void); + +extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); + +extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); + +#endif