From patchwork Tue Aug 16 17:52:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Brown X-Patchwork-Id: 1072142 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7GHsUYe010741 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 16 Aug 2011 17:54:51 GMT Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QtNpt-0000Be-MU; Tue, 16 Aug 2011 17:53:58 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QtNps-00008w-38; Tue, 16 Aug 2011 17:53:56 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QtNox-0008Nd-Ky for linux-arm-kernel@lists.infradead.org; Tue, 16 Aug 2011 17:53:01 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6440"; a="110727528" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 16 Aug 2011 10:52:30 -0700 Received: from codeaurora.org (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 4434A10004D1; Tue, 16 Aug 2011 10:52:30 -0700 (PDT) From: David Brown To: Russell King , David Brown , Daniel Walker , Bryan Huntsman Subject: [PATCH v2 4/4] ARM: msm: Describe MSM 8660 SURF FPGA registers in DT Date: Tue, 16 Aug 2011 10:52:16 -0700 Message-Id: <1313517136-27414-5-git-send-email-davidb@codeaurora.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1313517136-27414-1-git-send-email-davidb@codeaurora.org> References: <1313517136-27414-1-git-send-email-davidb@codeaurora.org> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110816_135300_059726_3A8427A1 X-CRM114-Status: GOOD ( 20.79 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] Cc: linux-arm-msm@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 16 Aug 2011 17:54:51 +0000 (UTC) The MSM 8660 SURF development board contains a register-accessible FPGA. By default, this FPGA configures the first UART in output-only mode. On this target, reconfigure this FPGA to enable the UART to be bidirectional. Signed-off-by: David Brown --- arch/arm/boot/dts/msm8660-surf.dts | 5 +++ arch/arm/mach-msm/board-msm8x60.c | 48 +++++++++++++++++++++++++++++++++--- 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 15ded0d..3591c94 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -21,4 +21,9 @@ <0x19c00000 0x1000>; interrupts = <195>; }; + + qcom,fpga@1d000000 { + compatible = "qcom,msm8660-surf-fpga"; + reg = < 0x1d000000 0x1000 >; + }; }; diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 10fa8f6..db973bb 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -58,8 +58,51 @@ static void __init msm8x60_init_irq(void) } } +static void __init msm8660_surf_fpga_init(void *fpga_mem) +{ + /* Advanced mode */ + writew(0xFFFF, fpga_mem + 0x15C); + /* FPGA_UART_SEL */ + writew(0, fpga_mem + 0x172); + /* FPGA_GPIO_CONFIG_117 */ + writew(1, fpga_mem + 0xEA); + /* FPGA_GPIO_CONFIG_118 */ + writew(1, fpga_mem + 0xEC); + dmb(); + iounmap(fpga_mem); +} + +static void __init msm8660_surf_fpga_init_platform(void) +{ + /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */ + void *fpga_mem = ioremap(0x1D000000, SZ_4K); + msm8660_surf_fpga_init(fpga_mem); +} + +#ifdef CONFIG_OF +static void __init msm8660_surf_fpga_init_dt(void) +{ + struct device_node *node; + void *fpga_mem; + + node = of_find_compatible_node(NULL, NULL, "qcom,msm8660-surf-fpga"); + if (!node) + return; + + fpga_mem = of_iomap(node, 0); + of_node_put(node); + if (!fpga_mem) { + printk(KERN_ERR "%s: Can't map fpga registers\n", __func__); + return; + } + + msm8660_surf_fpga_init(fpga_mem); +} +#endif + static void __init msm8x60_init(void) { + msm8660_surf_fpga_init_platform(); } #ifdef CONFIG_OF @@ -81,10 +124,7 @@ static void __init msm8x60_dt_init(void) if (node) irq_domain_add_simple(node, GIC_SPI_START); - if (of_machine_is_compatible("qcom,msm8660-surf")) { - printk(KERN_INFO "Init surf UART registers\n"); - msm8x60_init_uart12dm(); - } + msm8660_surf_fpga_init_dt(); of_platform_populate(NULL, of_default_bus_match_table, msm_auxdata_lookup, NULL);