| Message ID | 1313526898-19920-2-git-send-email-robherring2@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Rob, On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: > From: Rob Herring <rob.herring@calxeda.com> > > This adds the devicetree source and documentation for the Calxeda highbank > platform. > > Signed-off-by: Rob Herring <rob.herring@calxeda.com> > --- > Documentation/devicetree/bindings/arm/calxeda.txt | 8 + > arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ > 2 files changed, 220 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt > create mode 100644 arch/arm/boot/dts/highbank.dts > > diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt > new file mode 100644 > index 0000000..4755caa > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/calxeda.txt > @@ -0,0 +1,8 @@ > +Calxeda Highbank Platforms Device Tree Bindings > +----------------------------------------------- > + > +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following > +properties. > + > +Required root node properties: > + - compatible = "calxeda,highbank"; > diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts > new file mode 100644 > index 0000000..2dd3b7b > --- /dev/null > +++ b/arch/arm/boot/dts/highbank.dts > @@ -0,0 +1,212 @@ > +/* > + * Copyright 2011 Calxeda, Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +/dts-v1/; > + > +/* First 4KB has pen for secondary cores. */ > +/memreserve/ 0x00000000 0x0001000; > + I failed to find the "pen" handling in the whole patch series. Am I missing anything?
Hi Rob, > -----Original Message----- > From: linux-arm-kernel-bounces@lists.infradead.org [mailto:linux-arm- > kernel-bounces@lists.infradead.org] On Behalf Of Rob Herring > Sent: 16 August 2011 21:35 > To: linux-arm-kernel@lists.infradead.org > Cc: Rob Herring > Subject: [PATCH 1/6] ARM: highbank: add devicetree source > > From: Rob Herring <rob.herring@calxeda.com> > > This adds the devicetree source and documentation for the Calxeda > highbank > platform. > > Signed-off-by: Rob Herring <rob.herring@calxeda.com> > --- > Documentation/devicetree/bindings/arm/calxeda.txt | 8 + > arch/arm/boot/dts/highbank.dts | 212 > +++++++++++++++++++++ > 2 files changed, 220 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt > create mode 100644 arch/arm/boot/dts/highbank.dts ... > + L2: l2-cache { > + compatible = "arm,pl310-cache"; > + reg = <0xfff12000 0x1000>; > + interrupts = <102>; > + cache-unified; > + cache-level = <2>; > + }; Currently, the binding documentation sitting in Russell's for-next branch doesn't have the interrupts property we discussed previously: http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html I posted a patch to add it to the documentation, but no-one responded: http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007349.html Can I take your use of the property as an ack? How do we get this merged? Thanks, Mark.
Shawn, On 08/17/2011 02:27 AM, Shawn Guo wrote: > Hi Rob, > > On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: >> From: Rob Herring <rob.herring@calxeda.com> >> >> This adds the devicetree source and documentation for the Calxeda highbank >> platform. >> >> Signed-off-by: Rob Herring <rob.herring@calxeda.com> >> --- >> Documentation/devicetree/bindings/arm/calxeda.txt | 8 + >> arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ >> 2 files changed, 220 insertions(+), 0 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt >> create mode 100644 arch/arm/boot/dts/highbank.dts >> >> diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt >> new file mode 100644 >> index 0000000..4755caa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/calxeda.txt >> @@ -0,0 +1,8 @@ >> +Calxeda Highbank Platforms Device Tree Bindings >> +----------------------------------------------- >> + >> +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following >> +properties. >> + >> +Required root node properties: >> + - compatible = "calxeda,highbank"; >> diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts >> new file mode 100644 >> index 0000000..2dd3b7b >> --- /dev/null >> +++ b/arch/arm/boot/dts/highbank.dts >> @@ -0,0 +1,212 @@ >> +/* >> + * Copyright 2011 Calxeda, Inc. >> + * >> + * This program is free software; you can redistribute it and/or modify it >> + * under the terms and conditions of the GNU General Public License, >> + * version 2, as published by the Free Software Foundation. >> + * >> + * This program is distributed in the hope it will be useful, but WITHOUT >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or >> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for >> + * more details. >> + * >> + * You should have received a copy of the GNU General Public License along with >> + * this program. If not, see <http://www.gnu.org/licenses/>. >> + */ >> + >> +/dts-v1/; >> + >> +/* First 4KB has pen for secondary cores. */ >> +/memreserve/ 0x00000000 0x0001000; >> + > I failed to find the "pen" handling in the whole patch series. Am I > missing anything? > In highbank.c: +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) + +void highbank_set_cpu_jump(int cpu, void *jump_addr) +{ + writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), + HB_JUMP_TABLE_PHYS(cpu) + 15); +} Rob
Mark, On 08/17/2011 04:27 AM, Mark Rutland wrote: > Hi Rob, > >> -----Original Message----- >> From: linux-arm-kernel-bounces@lists.infradead.org [mailto:linux-arm- >> kernel-bounces@lists.infradead.org] On Behalf Of Rob Herring >> Sent: 16 August 2011 21:35 >> To: linux-arm-kernel@lists.infradead.org >> Cc: Rob Herring >> Subject: [PATCH 1/6] ARM: highbank: add devicetree source >> >> From: Rob Herring <rob.herring@calxeda.com> >> >> This adds the devicetree source and documentation for the Calxeda >> highbank >> platform. >> >> Signed-off-by: Rob Herring <rob.herring@calxeda.com> >> --- >> Documentation/devicetree/bindings/arm/calxeda.txt | 8 + >> arch/arm/boot/dts/highbank.dts | 212 >> +++++++++++++++++++++ >> 2 files changed, 220 insertions(+), 0 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt >> create mode 100644 arch/arm/boot/dts/highbank.dts > > ... > >> + L2: l2-cache { >> + compatible = "arm,pl310-cache"; >> + reg = <0xfff12000 0x1000>; >> + interrupts = <102>; >> + cache-unified; >> + cache-level = <2>; >> + }; > > Currently, the binding documentation sitting in Russell's for-next branch > doesn't have the interrupts property we discussed previously: > http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html > > I posted a patch to add it to the documentation, but no-one responded: > http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007349.html > > Can I take your use of the property as an ack? > Yes, sorry forgot about it. Acked-by: Rob Herring <rob.herring@calxeda.com> > How do we get this merged? Add to Russell's patch system or perhaps in Will's tree. Rob
Hi Mark, On Wed, Aug 17, 2011 at 03:08:38PM +0100, Rob Herring wrote: > On 08/17/2011 04:27 AM, Mark Rutland wrote: > > How do we get this merged? > > Add to Russell's patch system or perhaps in Will's tree. Stick it in Russell's patch system with my Ack (since I don't have any other fixes currently queued). Thanks, Will
On Wed, Aug 17, 2011 at 08:49:41AM -0500, Rob Herring wrote: > Shawn, > > On 08/17/2011 02:27 AM, Shawn Guo wrote: > > Hi Rob, > > > > On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: > >> From: Rob Herring <rob.herring@calxeda.com> > >> > >> This adds the devicetree source and documentation for the Calxeda highbank > >> platform. > >> > >> Signed-off-by: Rob Herring <rob.herring@calxeda.com> > >> --- > >> Documentation/devicetree/bindings/arm/calxeda.txt | 8 + > >> arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ > >> 2 files changed, 220 insertions(+), 0 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt > >> create mode 100644 arch/arm/boot/dts/highbank.dts > >> > >> diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt > >> new file mode 100644 > >> index 0000000..4755caa > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/arm/calxeda.txt > >> @@ -0,0 +1,8 @@ > >> +Calxeda Highbank Platforms Device Tree Bindings > >> +----------------------------------------------- > >> + > >> +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following > >> +properties. > >> + > >> +Required root node properties: > >> + - compatible = "calxeda,highbank"; > >> diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts > >> new file mode 100644 > >> index 0000000..2dd3b7b > >> --- /dev/null > >> +++ b/arch/arm/boot/dts/highbank.dts > >> @@ -0,0 +1,212 @@ > >> +/* > >> + * Copyright 2011 Calxeda, Inc. > >> + * > >> + * This program is free software; you can redistribute it and/or modify it > >> + * under the terms and conditions of the GNU General Public License, > >> + * version 2, as published by the Free Software Foundation. > >> + * > >> + * This program is distributed in the hope it will be useful, but WITHOUT > >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > >> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > >> + * more details. > >> + * > >> + * You should have received a copy of the GNU General Public License along with > >> + * this program. If not, see <http://www.gnu.org/licenses/>. > >> + */ > >> + > >> +/dts-v1/; > >> + > >> +/* First 4KB has pen for secondary cores. */ > >> +/memreserve/ 0x00000000 0x0001000; > >> + > > I failed to find the "pen" handling in the whole patch series. Am I > > missing anything? > > > > In highbank.c: > > +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) > +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) > + > +void highbank_set_cpu_jump(int cpu, void *jump_addr) > +{ > + writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); > + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); > + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), > + HB_JUMP_TABLE_PHYS(cpu) + 15); > +} > Ah, ok, the 'pen' you meant is the entry address of secondary cores. I thought of something like 'pen_release' in plat-versatile/platsmp.c. So you do not need 'boot_lock' and 'pen_release' stuff to sync secondary cores with the primary one (like all other smp platforms do)?
Hi Rob, On Wed, Aug 17, 2011 at 02:49:41PM +0100, Rob Herring wrote: > In highbank.c: > > +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) > +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) > + > +void highbank_set_cpu_jump(int cpu, void *jump_addr) > +{ > + writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); > + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); > + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), > + HB_JUMP_TABLE_PHYS(cpu) + 15); > +} I don't suppose you guys can boot on a CPU other than 0 can you? That would be really handy for testing my cpu-mapping patch series :) Will
On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: > From: Rob Herring <rob.herring@calxeda.com> > > This adds the devicetree source and documentation for the Calxeda highbank > platform. > > Signed-off-by: Rob Herring <rob.herring@calxeda.com> > --- > Documentation/devicetree/bindings/arm/calxeda.txt | 8 + > arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ > 2 files changed, 220 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt > create mode 100644 arch/arm/boot/dts/highbank.dts > > diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt > new file mode 100644 > index 0000000..4755caa > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/calxeda.txt > @@ -0,0 +1,8 @@ > +Calxeda Highbank Platforms Device Tree Bindings > +----------------------------------------------- > + > +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following > +properties. > + > +Required root node properties: > + - compatible = "calxeda,highbank"; > diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts > new file mode 100644 > index 0000000..2dd3b7b > --- /dev/null > +++ b/arch/arm/boot/dts/highbank.dts > @@ -0,0 +1,212 @@ > +/* > + * Copyright 2011 Calxeda, Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +/dts-v1/; > + > +/* First 4KB has pen for secondary cores. */ > +/memreserve/ 0x00000000 0x0001000; > + > +/ { > + model = "Calxeda Highbank"; > + compatible = "calxeda,highbank"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a9"; > + reg = <0>; > + next-level-cache = <&L2>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a9"; > + reg = <1>; > + next-level-cache = <&L2>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a9"; > + reg = <2>; > + next-level-cache = <&L2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a9"; > + reg = <3>; > + next-level-cache = <&L2>; > + }; > + }; > + I'm not sure if this whole "cpus" stuff is needed, I do not see any code playing with it.
On 08/20/2011 04:51 AM, Shawn Guo wrote: > On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: >> From: Rob Herring <rob.herring@calxeda.com> >> >> This adds the devicetree source and documentation for the Calxeda highbank >> platform. >> >> Signed-off-by: Rob Herring <rob.herring@calxeda.com> >> --- >> Documentation/devicetree/bindings/arm/calxeda.txt | 8 + >> arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ >> 2 files changed, 220 insertions(+), 0 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt >> create mode 100644 arch/arm/boot/dts/highbank.dts >> >> diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt >> new file mode 100644 >> index 0000000..4755caa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/calxeda.txt >> @@ -0,0 +1,8 @@ >> +Calxeda Highbank Platforms Device Tree Bindings >> +----------------------------------------------- >> + >> +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following >> +properties. >> + >> +Required root node properties: >> + - compatible = "calxeda,highbank"; >> diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts >> new file mode 100644 >> index 0000000..2dd3b7b >> --- /dev/null >> +++ b/arch/arm/boot/dts/highbank.dts >> @@ -0,0 +1,212 @@ >> +/* >> + * Copyright 2011 Calxeda, Inc. >> + * >> + * This program is free software; you can redistribute it and/or modify it >> + * under the terms and conditions of the GNU General Public License, >> + * version 2, as published by the Free Software Foundation. >> + * >> + * This program is distributed in the hope it will be useful, but WITHOUT >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or >> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for >> + * more details. >> + * >> + * You should have received a copy of the GNU General Public License along with >> + * this program. If not, see <http://www.gnu.org/licenses/>. >> + */ >> + >> +/dts-v1/; >> + >> +/* First 4KB has pen for secondary cores. */ >> +/memreserve/ 0x00000000 0x0001000; >> + >> +/ { >> + model = "Calxeda Highbank"; >> + compatible = "calxeda,highbank"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu@0 { >> + compatible = "arm,cortex-a9"; >> + reg = <0>; >> + next-level-cache = <&L2>; >> + }; >> + >> + cpu@1 { >> + compatible = "arm,cortex-a9"; >> + reg = <1>; >> + next-level-cache = <&L2>; >> + }; >> + >> + cpu@2 { >> + compatible = "arm,cortex-a9"; >> + reg = <2>; >> + next-level-cache = <&L2>; >> + }; >> + >> + cpu@3 { >> + compatible = "arm,cortex-a9"; >> + reg = <3>; >> + next-level-cache = <&L2>; >> + }; >> + }; >> + > I'm not sure if this whole "cpus" stuff is needed, I do not see any > code playing with it. > Prior reviews of dts's by Grant and others suggested putting this in. Rob
On 08/17/2011 12:52 PM, Will Deacon wrote: > Hi Rob, > > On Wed, Aug 17, 2011 at 02:49:41PM +0100, Rob Herring wrote: >> In highbank.c: >> >> +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) >> +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) >> + >> +void highbank_set_cpu_jump(int cpu, void *jump_addr) >> +{ >> + writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); >> + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); >> + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), >> + HB_JUMP_TABLE_PHYS(cpu) + 15); >> +} > > I don't suppose you guys can boot on a CPU other than 0 can you? That would be > really handy for testing my cpu-mapping patch series :) > We probably can with a little work to the boot code. Rob
On 08/17/2011 09:51 AM, Shawn Guo wrote: > On Wed, Aug 17, 2011 at 08:49:41AM -0500, Rob Herring wrote: >> Shawn, >> >> On 08/17/2011 02:27 AM, Shawn Guo wrote: >>> Hi Rob, >>> >>> On Tue, Aug 16, 2011 at 03:34:53PM -0500, Rob Herring wrote: >>>> From: Rob Herring <rob.herring@calxeda.com> >>>> >>>> This adds the devicetree source and documentation for the Calxeda highbank >>>> platform. >>>> >>>> Signed-off-by: Rob Herring <rob.herring@calxeda.com> >>>> --- >>>> Documentation/devicetree/bindings/arm/calxeda.txt | 8 + >>>> arch/arm/boot/dts/highbank.dts | 212 +++++++++++++++++++++ >>>> 2 files changed, 220 insertions(+), 0 deletions(-) >>>> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt >>>> create mode 100644 arch/arm/boot/dts/highbank.dts >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt >>>> new file mode 100644 >>>> index 0000000..4755caa >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/arm/calxeda.txt >>>> @@ -0,0 +1,8 @@ >>>> +Calxeda Highbank Platforms Device Tree Bindings >>>> +----------------------------------------------- >>>> + >>>> +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following >>>> +properties. >>>> + >>>> +Required root node properties: >>>> + - compatible = "calxeda,highbank"; >>>> diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts >>>> new file mode 100644 >>>> index 0000000..2dd3b7b >>>> --- /dev/null >>>> +++ b/arch/arm/boot/dts/highbank.dts >>>> @@ -0,0 +1,212 @@ >>>> +/* >>>> + * Copyright 2011 Calxeda, Inc. >>>> + * >>>> + * This program is free software; you can redistribute it and/or modify it >>>> + * under the terms and conditions of the GNU General Public License, >>>> + * version 2, as published by the Free Software Foundation. >>>> + * >>>> + * This program is distributed in the hope it will be useful, but WITHOUT >>>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or >>>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for >>>> + * more details. >>>> + * >>>> + * You should have received a copy of the GNU General Public License along with >>>> + * this program. If not, see <http://www.gnu.org/licenses/>. >>>> + */ >>>> + >>>> +/dts-v1/; >>>> + >>>> +/* First 4KB has pen for secondary cores. */ >>>> +/memreserve/ 0x00000000 0x0001000; >>>> + >>> I failed to find the "pen" handling in the whole patch series. Am I >>> missing anything? >>> >> >> In highbank.c: >> >> +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) >> +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) >> + >> +void highbank_set_cpu_jump(int cpu, void *jump_addr) >> +{ >> + writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); >> + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); >> + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), >> + HB_JUMP_TABLE_PHYS(cpu) + 15); >> +} >> > Ah, ok, the 'pen' you meant is the entry address of secondary cores. > I thought of something like 'pen_release' in plat-versatile/platsmp.c. > So you do not need 'boot_lock' and 'pen_release' stuff to sync secondary > cores with the primary one (like all other smp platforms do)? > The kernel pen code is only needed for cores that don't reset on hot unplug and just go to wfi. All other smp platforms just cut and paste the same code. Rob
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt new file mode 100644 index 0000000..4755caa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.txt @@ -0,0 +1,8 @@ +Calxeda Highbank Platforms Device Tree Bindings +----------------------------------------------- + +Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following +properties. + +Required root node properties: + - compatible = "calxeda,highbank"; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts new file mode 100644 index 0000000..2dd3b7b --- /dev/null +++ b/arch/arm/boot/dts/highbank.dts @@ -0,0 +1,212 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + chosen { + bootargs = "console=ttyAMA0"; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <1>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + + gicppi0: gic-ppi@0 { + compatible = "arm,cortex-a9-gic-ppi"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0>; + }; + gicppi1: gic-ppi@1 { + compatible = "arm,cortex-a9-gic-ppi"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + timer@fff10600 { + compatible = "arm,smp-twd"; + reg = <0xfff10600 0x20>; + interrupt-parent = <&gicppi0>; + interrupts = <29>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-wdt"; + reg = <0xfff10620 0x20>; + interrupt-parent = <&gicppi0>; + interrupts = <30>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <102>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <108 107 106 105>; + }; + + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <115>; + }; + + sdhci@ffe0e000 { + compatible = "calxeda,hb-sdhci"; + reg = <0xffe0e000 0x1000>; + interrupts = <122>; + }; + + ipc@fff20000 { + compatible = "arm,pl320", "arm,primecell"; + reg = <0xfff20000 0x1000>; + interrupts = <39>; + }; + + gpioe: gpio@fff30000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff30000 0x1000>; + interrupts = <46>; + }; + + gpiof: gpio@fff31000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff31000 0x1000>; + interrupts = <47>; + }; + + gpiog: gpio@fff32000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff32000 0x1000>; + interrupts = <48>; + }; + + gpioh: gpio@fff33000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff33000 0x1000>; + interrupts = <49>; + }; + + timer { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfff34000 0x1000>; + interrupts = <50>; + }; + + rtc@fff35000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0xfff35000 0x1000>; + interrupts = <51>; + }; + + serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xfff36000 0x1000>; + interrupts = <52>; + }; + + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <56>; + reg-size = <4>; + reg-spacing = <4>; + }; + + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + }; + + dma@fff3d000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfff3d000 0x1000>; + interrupts = <124>; + }; + }; +};