From patchwork Wed Aug 17 11:47:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamie Iles X-Patchwork-Id: 1073702 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7HBmgfM015186 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 17 Aug 2011 11:49:04 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QtebT-0006gg-8r; Wed, 17 Aug 2011 11:48:12 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QtebS-0003lp-K0; Wed, 17 Aug 2011 11:48:10 +0000 Received: from mail-ww0-f49.google.com ([74.125.82.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qteau-0003fT-Oc for linux-arm-kernel@lists.infradead.org; Wed, 17 Aug 2011 11:47:39 +0000 Received: by wwf10 with SMTP id 10so646832wwf.18 for ; Wed, 17 Aug 2011 04:47:35 -0700 (PDT) Received: by 10.227.10.201 with SMTP id q9mr763010wbq.68.1313581655456; Wed, 17 Aug 2011 04:47:35 -0700 (PDT) Received: from localhost (gw-ba1.picochip.com [94.175.234.108]) by mx.google.com with ESMTPS id fm9sm845725wbb.10.2011.08.17.04.47.34 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Aug 2011 04:47:35 -0700 (PDT) From: Jamie Iles To: devicetree-discuss@lists.ozlabs.org Subject: [RFC PATCH 2/2] arm/tegra: Add device tree support to pinmux driver Date: Wed, 17 Aug 2011 12:47:28 +0100 Message-Id: <1313581648-22303-3-git-send-email-jamie@jamieiles.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1313581648-22303-1-git-send-email-jamie@jamieiles.com> References: <1313581648-22303-1-git-send-email-jamie@jamieiles.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110817_074737_129919_EBB1EF5A X-CRM114-Status: GOOD ( 17.65 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] Cc: linux@arm.linux.org.uk, sshtylyov@mvista.com, konkers@android.com, marek.belisko@gmail.com, linus.walleij@linaro.org, Jamie Iles , grant.likely@secretlab.ca, linux-arm-kernel@lists.infradead.org, ccross@android.com, swarren@nvidia.com, shawn.guo@freescale.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 17 Aug 2011 11:49:04 +0000 (UTC) From: Stephen Warren [ j.iles: converted to generic of_pinmux_parse() ] Signed-off-by: Stephen Warren Signed-off-by: Jamie Iles --- arch/arm/mach-tegra/pinmux.c | 240 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 240 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index ed316f9..cd540eb 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include @@ -124,6 +126,21 @@ static const char *pingroup_name(enum tegra_pingroup pg) return pingroups[pg].name; } +#ifdef CONFIG_OF +static int pingroup_enum(const char *name, enum tegra_pingroup *pg_out) +{ + int pg; + + for (pg = 0; pg < TEGRA_MAX_PINGROUP; pg++) + if (!strcasecmp(name, tegra_soc_pingroups[pg].name)) { + *pg_out = pg; + return 0; + } + + return -EINVAL; +} +#endif + static const char *func_name(enum tegra_mux_func func) { if (func == TEGRA_MUX_RSVD1) @@ -147,6 +164,41 @@ static const char *func_name(enum tegra_mux_func func) return tegra_mux_names[func]; } +#ifdef CONFIG_OF +static int func_enum(const char *name, enum tegra_mux_func *func_out) +{ + int func; + + if (!strcasecmp(name, "RSVD1")) { + *func_out = TEGRA_MUX_RSVD1; + return 0; + } + if (!strcasecmp(name, "RSVD2")) { + *func_out = TEGRA_MUX_RSVD2; + return 0; + } + if (!strcasecmp(name, "RSVD3")) { + *func_out = TEGRA_MUX_RSVD3; + return 0; + } + if (!strcasecmp(name, "RSVD4")) { + *func_out = TEGRA_MUX_RSVD4; + return 0; + } + if (!strcasecmp(name, "NONE")) { + *func_out = TEGRA_MUX_NONE; + return 0; + } + + for (func = 0; func < TEGRA_MAX_MUX; func++) + if (!strcasecmp(name, tegra_mux_names[func])) { + *func_out = func; + return 0; + } + + return -EINVAL; +} +#endif static const char *tri_name(unsigned long val) { @@ -329,6 +381,22 @@ static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) return drive_pingroups[pg].name; } +#ifdef CONFIG_OF +static int drive_pinmux_enum(const char *name, + enum tegra_drive_pingroup *pg_out) +{ + int pg; + + for (pg = 0; pg < TEGRA_MAX_DRIVE_PINGROUP; pg++) + if (!strcasecmp(name, drive_pingroups[pg].name)) { + *pg_out = pg; + return 0; + } + + return -EINVAL; +} +#endif + static const char *enable_name(unsigned long val) { return val ? "ENABLE" : "DISABLE"; @@ -666,15 +734,187 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } } +#ifdef CONFIG_OF +static int __init tegra_pinmux_dt_configure(const struct of_pinmux_ctrl *ctrl, + const struct of_pinmux_cfg *config) +{ + struct tegra_pingroup_config tegra_config; + int ret; + + ret = pingroup_enum(config->pin->name, &tegra_config.pingroup); + if (ret < 0) { + pr_err("invalid pingroup name (%s)\n", config->pin->name); + return ret; + } + + ret = func_enum(config->function, &tegra_config.func); + if (ret < 0) { + pr_err("invalid function (%s)\n", config->function); + return ret; + } + + if (config->flags & OF_PINMUX_PULL_UP) + tegra_config.pupd = TEGRA_PUPD_PULL_UP; + else if (config->flags & OF_PINMUX_PULL_DOWN) + tegra_config.pupd = TEGRA_PUPD_PULL_DOWN; + else + tegra_config.pupd = TEGRA_PUPD_NORMAL; + + tegra_config.tristate = (config->flags & OF_PINMUX_TRISTATE) ? + TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL; + + tegra_pinmux_config_pingroup(&tegra_config); + + return 0; +} +static void __init tegra_pinmux_parse_mux_groups( + struct platform_device *pdev, + struct device_node *mux_node) +{ + struct of_pinmux_ctrl tegra_pinmux_ctrl = { + .pinmux = mux_node, + .configure = tegra_pinmux_dt_configure, + }; + + if (of_pinmux_parse(&tegra_pinmux_ctrl)) + pr_err("failed to parse pinmux configuration\n"); +} + +static void __init tegra_pinmux_parse_drive_groups( + struct platform_device *pdev, + struct device_node *drive_node) +{ + struct device_node *node; + + for_each_child_of_node(drive_node, node) { + enum tegra_drive_pingroup pg; + enum tegra_hsm hsm; + enum tegra_schmitt schmitt; + enum tegra_drive drive; + enum tegra_pull_strength pull_down; + enum tegra_pull_strength pull_up; + enum tegra_slew slew_rising; + enum tegra_slew slew_falling; + int ret; + + ret = drive_pinmux_enum(node->name, &pg); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Invalid pingroup name\n", + node->name); + continue; + } + + if (of_find_property(node, "nvidia,high-speed-mode", NULL)) + hsm = TEGRA_HSM_ENABLE; + else + hsm = TEGRA_HSM_DISABLE; + + if (of_find_property(node, "nvidia,schmitt", NULL)) + schmitt = TEGRA_SCHMITT_ENABLE; + else + schmitt = TEGRA_SCHMITT_DISABLE; + + ret = of_property_read_u32(node, "nvidia,drive-power", &drive); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Missing property " + "nvidia,drive-power\n", + node->name); + continue; + } + + ret = of_property_read_u32(node, "nvidia,pull-down-strength", + &pull_down); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Missing property " + "nvidia,pull-down-strength\n", + node->name); + continue; + } + + ret = of_property_read_u32(node, "nvidia,pull-up-strength", + &pull_up); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Missing property " + "nvidia,pull-up-strength\n", + node->name); + continue; + } + + ret = of_property_read_u32(node, "nvidia,slew-rate-rising", + &slew_rising); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Missing property " + "nvidia,slew_rate-rising\n", + node->name); + continue; + } + + ret = of_property_read_u32(node, "nvidia,slew-rate-falling", + &slew_rising); + if (ret < 0) { + dev_err(&pdev->dev, + "(drive) %s: Missing property " + "nvidia,slew_rate-falling\n", + node->name); + continue; + } + + dev_dbg(&pdev->dev, + "(drive) %s: hsm %d schmitt %d drive %d " + "pull_down %d pull_up %d slew_r %d slew_f %d\n", + node->name, + hsm, schmitt, drive, + pull_down, pull_up, + slew_rising, slew_falling); + + tegra_drive_pinmux_config_pingroup(pg, hsm, schmitt, drive, + pull_down, pull_up, + slew_rising, slew_falling); + } +} + +static void __init tegra_pinmux_probe_dt(struct platform_device *pdev) +{ + struct device_node *node; + + for_each_child_of_node(pdev->dev.of_node, node) { + if (!strcmp(node->name, "nvidia,mux-groups")) + tegra_pinmux_parse_mux_groups(pdev, node); + else if (!strcmp(node->name, "nvidia,drive-groups")) + tegra_pinmux_parse_drive_groups(pdev, node); + else + dev_err(&pdev->dev, "%s: Unknown child node\n", + node->name); + } +} +#else +static inline void __init tegra_pinmux_probe_dt(struct platform_device *pdev) +{ +} +#endif + static int __init tegra_pinmux_probe(struct platform_device *pdev) { + tegra_pinmux_probe_dt(pdev); + return 0; } +static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { + { .compatible = "nvidia,tegra20-pinmux", }, + { }, +}; + static struct platform_driver tegra_pinmux_driver = { .driver = { .name = "tegra-pinmux", .owner = THIS_MODULE, + .of_match_table = tegra_pinmux_of_match, }, .probe = tegra_pinmux_probe, };