From patchwork Wed Aug 24 09:23:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1091662 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7O9P8Aw006923 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 24 Aug 2011 09:25:29 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qw9hK-0007L3-TJ; Wed, 24 Aug 2011 09:24:35 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qw9hK-0007OR-EI; Wed, 24 Aug 2011 09:24:34 +0000 Received: from eu1sys200aog115.obsmtp.com ([207.126.144.139]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qw9gr-0007In-QK for linux-arm-kernel@lists.infradead.org; Wed, 24 Aug 2011 09:24:07 +0000 Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKTlTDMULgKYxVyXpNhwc1ZGjaRxbETBdx@postini.com; Wed, 24 Aug 2011 09:24:05 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4434B68; Wed, 24 Aug 2011 09:24:00 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id CE9FB4E; Wed, 24 Aug 2011 09:23:59 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 689B2A807B; Wed, 24 Aug 2011 11:23:55 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 24 Aug 2011 11:23:58 +0200 From: Linus Walleij To: Subject: [PATCH 3/3] mach-ux500: unlock I&D l2x0 caches before init Date: Wed, 24 Aug 2011 11:23:55 +0200 Message-ID: <1314177835-19186-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110824_052406_136241_DD68F4F4 X-CRM114-Status: GOOD ( 13.81 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.139 listed in list.dnswl.org] Cc: Linus Walleij , Rabin Vincent , Lee Jones , Srinidhi Kasagar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 24 Aug 2011 09:25:29 +0000 (UTC) From: Linus Walleij Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. Cc: Srinidhi Kasagar Cc: Rabin Vincent Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cache-l2x0.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index aa2d77f..f5c31f1 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -59,6 +59,16 @@ static int ux500_l2x0_init(void) else ux500_unknown_soc(); + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. + */ + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_D) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); + + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_I) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); + /* 64KB way size, 8 way associativity, force WA */ l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);