From patchwork Wed Aug 24 13:09:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 1092352 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7ODCr3N009451 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 24 Aug 2011 13:13:14 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QwDFV-0004In-8Z; Wed, 24 Aug 2011 13:12:06 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QwDFU-0004g2-7R; Wed, 24 Aug 2011 13:12:04 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QwDEa-0004Tw-B9 for linux-arm-kernel@lists.infradead.org; Wed, 24 Aug 2011 13:11:10 +0000 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7ODB7vT013123 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 24 Aug 2011 08:11:07 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep33.itg.ti.com (8.13.7/8.13.8) with ESMTP id p7ODB6U0011864; Wed, 24 Aug 2011 08:11:06 -0500 (CDT) Received: from DFLE70.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7ODB6Tx027610; Wed, 24 Aug 2011 08:11:06 -0500 (CDT) Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle70.ent.ti.com (128.247.5.40) with Microsoft SMTP Server id 14.1.323.3; Wed, 24 Aug 2011 08:11:06 -0500 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7ODA8He023561; Wed, 24 Aug 2011 08:11:04 -0500 From: Benoit Cousson To: , Subject: [RFC PATCH 04/10] arm/dts: OMAP4: Add mpu, dsp and iva nodes Date: Wed, 24 Aug 2011 15:09:10 +0200 Message-ID: <1314191356-10963-5-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1314191356-10963-1-git-send-email-b-cousson@ti.com> References: <1314191356-10963-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110824_091108_596387_1C65446A X-CRM114-Status: GOOD ( 15.13 ) X-Spam-Score: -2.8 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [198.47.26.152 listed in list.dnswl.org] -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, Benoit Cousson , manjugk@ti.com, devicetree-discuss@lists.ozlabs.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 24 Aug 2011 13:13:14 +0000 (UTC) Add nodes for devices used by PM code (mpu, dsp, iva). Add an empty cpus node as well as recommended in the DT spec. Remove mpu, dsp, iva devices init if CONFIG_OF is defined. Ideally the whole function should be removed. It will be doable as soon as the OMAP3 DT support will be added. Signed-off-by: Benoit Cousson Cc: Grant Likely Cc: Kevin Hilman --- arch/arm/boot/dts/omap4.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/mach-omap2/pm.c | 5 ++++- 2 files changed, 32 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 928a74c..a3efe76 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -25,11 +25,39 @@ }; /* + * XXX: The cpus node is mandatory, but since the CPUs are as well part + * of the mpu subsystem below, it is not clear where the information + * should be. Maybe here with a phandle inside the mpu? + */ + cpus { + }; + + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + hwmods = "mpu"; + cpu@0 { + compatible = "arm,cortex-a9"; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + }; + }; + + dsp { + compatible = "ti,omap4-c64", "ti,c64"; + hwmods = "dsp"; + }; + + iva { + compatible = "ti,ivahd", "ti,iva"; + hwmods = "iva"; + }; }; /* diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 832577a..ba4d187 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -49,15 +49,18 @@ static int _init_omap_device(char *name) */ static void omap2_init_processor_devices(void) { - _init_omap_device("mpu"); if (omap3_has_iva()) _init_omap_device("iva"); if (cpu_is_omap44xx()) { +#ifndef CONFIG_OF + _init_omap_device("mpu"); _init_omap_device("l3_main_1"); _init_omap_device("dsp"); _init_omap_device("iva"); +#endif } else { + _init_omap_device("mpu"); _init_omap_device("l3_main"); } }