From patchwork Fri Aug 26 05:35:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Liu X-Patchwork-Id: 1100172 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7Q5VZLk021758 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 26 Aug 2011 05:31:56 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qwp0M-0006TG-Hu; Fri, 26 Aug 2011 05:31:01 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qwp0H-0006o8-T2; Fri, 26 Aug 2011 05:30:53 +0000 Received: from db3ehsobe006.messaging.microsoft.com ([213.199.154.144] helo=DB3EHSOBE006.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qwoze-0006h4-VT for linux-arm-kernel@lists.infradead.org; Fri, 26 Aug 2011 05:30:16 +0000 Received: from mail62-db3-R.bigfish.com (10.3.81.245) by DB3EHSOBE006.bigfish.com (10.3.84.26) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Aug 2011 05:30:12 +0000 Received: from mail62-db3 (localhost.localdomain [127.0.0.1]) by mail62-db3-R.bigfish.com (Postfix) with ESMTP id 2FEE94A00B0; Fri, 26 Aug 2011 05:30:12 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail62-db3 (localhost.localdomain [127.0.0.1]) by mail62-db3 (MessageSwitch) id 1314336611916158_31814; Fri, 26 Aug 2011 05:30:11 +0000 (UTC) Received: from DB3EHSMHS017.bigfish.com (unknown [10.3.81.241]) by mail62-db3.bigfish.com (Postfix) with ESMTP id DBD116C004E; Fri, 26 Aug 2011 05:30:11 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS017.bigfish.com (10.3.87.117) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 26 Aug 2011 05:30:11 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.2; Fri, 26 Aug 2011 00:30:09 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7Q5U4oX001702; Fri, 26 Aug 2011 00:30:08 -0500 (CDT) From: Jason Liu To: Subject: [[PATCH v3 2/6] ARM: mx25: Print silicon revision on boot Date: Fri, 26 Aug 2011 13:35:19 +0800 Message-ID: <1314336923-25162-3-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> References: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110826_013015_254316_B6240DA7 X-CRM114-Status: GOOD ( 22.92 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.144 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 26 Aug 2011 05:31:56 +0000 (UTC) Silicon revision is useful information to have during kernel boot. Print the MX25 silicon revision. Signed-off-by: Fabio Estevam Signed-off-by: Jason Liu Cc: Sascha Hauer --- Resend: The patch first comes from Fabio, I did some change to use the generic function for displaying silicon revision --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/clock-imx25.c | 6 +++++ arch/arm/mach-imx/cpu-imx25.c | 41 +++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx25.h | 4 +++ 4 files changed, 52 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e9eb36d..0a5332c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c index e63e235..b0fec74c 100644 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c @@ -263,6 +263,7 @@ DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(iim_clk, 0, CCM_CGCR1, 26, NULL, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -310,6 +311,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) /* i.mx25 has the i.mx35 type sdma */ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) + _REGISTER_CLOCK(NULL, "iim", iim_clk) }; int __init mx25_clocks_init(void) @@ -334,6 +336,10 @@ int __init mx25_clocks_init(void) /* Clock source for gpt is ahb_div */ __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64); + clk_enable(&iim_clk); + imx_print_silicon_rev("i.MX25", mx25_revision()); + clk_disable(&iim_clk); + mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c new file mode 100644 index 0000000..6914bcb --- /dev/null +++ b/arch/arm/mach-imx/cpu-imx25.c @@ -0,0 +1,41 @@ +/* + * MX25 CPU type detection + * + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include + +static int mx25_cpu_rev = -1; + +static int mx25_read_cpu_rev(void) +{ + u32 rev; + + rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); + switch (rev) { + case 0x00: + return IMX_CHIP_REVISION_1_0; + case 0x01: + return IMX_CHIP_REVISION_1_1; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } +} + +int mx25_revision(void) +{ + if (mx25_cpu_rev == -1) + mx25_cpu_rev = mx25_read_cpu_rev(); + + return mx25_cpu_rev; +} +EXPORT_SYMBOL(mx25_revision); diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 087cd7a..8dcab80 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -104,4 +104,8 @@ #define MX25_DMA_REQ_SSI1_RX0 28 #define MX25_DMA_REQ_SSI1_TX0 29 +#ifndef __ASSEMBLY__ +extern int mx25_revision(void); +#endif + #endif /* ifndef __MACH_MX25_H__ */