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Fri, 26 Aug 2011 05:30:17 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Fri, 26 Aug 2011 00:30:16 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7Q5U4ob001702; Fri, 26 Aug 2011 00:30:15 -0500 (CDT) From: Jason Liu To: Subject: [[PATCH v3 6/6] ARM: mx5: use generic function for displaying silicon revision Date: Fri, 26 Aug 2011 13:35:23 +0800 Message-ID: <1314336923-25162-7-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> References: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110826_013021_134836_A50F96B1 X-CRM114-Status: GOOD ( 17.66 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.139 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 26 Aug 2011 05:33:01 +0000 (UTC) Update to use generic function for displaying silicon revision Tested on my mx53 loco board: CPU identified as i.MX53, silicon rev 2.0 Test on my mx51 babbage board: CPU identified as i.MX51, silicon rev 3.0 Signed-off-by: Jason Liu Cc: Fabio Estevam Cc: Sascha Hauer --- v2: print mx51 To3 correctly --- arch/arm/mach-mx5/clock-mx51-mx53.c | 6 +-- arch/arm/mach-mx5/cpu.c | 74 ++++++++--------------------------- 2 files changed, 19 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996..0e23e1d 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1548,9 +1548,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx51_revision(); + imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable(&iim_clk); - mx51_display_revision(); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy1_clk, &osc_clk); @@ -1592,9 +1591,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx53_revision(); + imx_print_silicon_rev("i.MX53", mx53_revision()); clk_disable(&iim_clk); - mx53_display_revision(); /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk, &pll2_sw_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 86f87da..5c53282 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -18,7 +18,7 @@ #include #include -static int cpu_silicon_rev = -1; +static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 #define MX50_HW_ADADIG_DIGPROG 0xB0 @@ -28,11 +28,14 @@ static int get_mx51_srev(void) void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (rev == 0x0) + switch (rev) { + case 0x0: return IMX_CHIP_REVISION_2_0; - else if (rev == 0x10) + case 0x10: return IMX_CHIP_REVISION_3_0; - return 0; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } } /* @@ -45,33 +48,13 @@ int mx51_revision(void) if (!cpu_is_mx51()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx51_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx51_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx51_revision); -void mx51_display_revision(void) -{ - int rev; - char *srev; - rev = mx51_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_3_0: - srev = IMX_CHIP_REVISION_3_0_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx51_display_revision); - #ifdef CONFIG_NEON /* @@ -121,10 +104,10 @@ int mx53_revision(void) if (!cpu_is_mx53()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx53_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx53_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); @@ -134,7 +117,7 @@ static int get_mx50_srev(void) u32 rev; if (!anatop) { - cpu_silicon_rev = -EINVAL; + mx5_cpu_rev = -EINVAL; return 0; } @@ -159,36 +142,13 @@ int mx50_revision(void) if (!cpu_is_mx50()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx50_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx50_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx50_revision); -void mx53_display_revision(void) -{ - int rev; - char *srev; - rev = mx53_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_1_0: - srev = IMX_CHIP_REVISION_1_0_STRING; - break; - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_2_1: - srev = IMX_CHIP_REVISION_2_1_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx53_display_revision); - static int __init post_cpu_init(void) { unsigned int reg;