From patchwork Mon Aug 29 17:35:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 1109192 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7THmgD3006492 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 29 Aug 2011 17:49:52 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qy5wi-00049f-Gk; Mon, 29 Aug 2011 17:48:29 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qy5wh-0006Gt-KU; Mon, 29 Aug 2011 17:48:27 +0000 Received: from na3sys009aog105.obsmtp.com ([74.125.149.75]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qy5kn-00058v-3S for linux-arm-kernel@lists.infradead.org; Mon, 29 Aug 2011 17:36:14 +0000 Received: from mail-yi0-f47.google.com ([209.85.218.47]) (using TLSv1) by na3sys009aob105.postini.com ([74.125.148.12]) with SMTP ID DSNKTlvOBh4g2SECgf/KsZFJBHXtu63xPH2e@postini.com; Mon, 29 Aug 2011 10:36:08 PDT Received: by mail-yi0-f47.google.com with SMTP id 28so4418469yia.34 for ; Mon, 29 Aug 2011 10:36:06 -0700 (PDT) Received: by 10.143.61.13 with SMTP id o13mr227363wfk.122.1314639366400; Mon, 29 Aug 2011 10:36:06 -0700 (PDT) Received: from localhost.localdomain (c-24-19-7-36.hsd1.wa.comcast.net. [24.19.7.36]) by mx.google.com with ESMTPS id m1sm19531524pbf.3.2011.08.29.10.36.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 29 Aug 2011 10:36:05 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Subject: [PATCH 21/22] OMAP2+: PRM: add register access functions for VC/VP Date: Mon, 29 Aug 2011 10:35:54 -0700 Message-Id: <1314639355-12713-22-git-send-email-khilman@ti.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1314639355-12713-1-git-send-email-khilman@ti.com> References: <1314639355-12713-1-git-send-email-khilman@ti.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110829_133609_573175_C05B5ADA X-CRM114-Status: GOOD ( 12.92 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.75 listed in list.dnswl.org] Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 29 Aug 2011 17:50:31 +0000 (UTC) On OMAP3+, the voltage controller (VC) and voltage processor (VP) are inside the PRM. Add some PRM helper functions for register access to these module registers. Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/prm2xxx_3xxx.c | 15 +++++++++++++++ arch/arm/mach-omap2/prm2xxx_3xxx.h | 8 ++++++++ arch/arm/mach-omap2/prm44xx.c | 22 ++++++++++++++++++++++ arch/arm/mach-omap2/prm44xx.h | 8 ++++++++ 4 files changed, 53 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 58c5c87..3b83763 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -197,3 +197,18 @@ void omap3_prm_vp_clear_txdone(u8 vp_id) omap2_prm_write_mod_reg(vp->tranxdone_status, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); } + +u32 omap3_prm_vcvp_read(u8 offset) +{ + return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); +} + +void omap3_prm_vcvp_write(u32 val, u8 offset) +{ + omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); +} + +u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +{ + return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); +} diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index 5112526..cef533d 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -307,7 +307,15 @@ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); u32 omap3_prm_vp_check_txdone(u8 vp_id); void omap3_prm_vp_clear_txdone(u8 vp_id); +/* + * OMAP3 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap3_prm_vcvp_read(u8 offset); +extern void omap3_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); #endif /* CONFIG_ARCH_OMAP4 */ + #endif /* diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 390e32c..495a31a 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -24,6 +24,8 @@ #include "vp.h" #include "prm44xx.h" #include "prm-regbits-44xx.h" +#include "prcm44xx.h" +#include "prminst44xx.h" /* PRM low-level functions */ @@ -99,3 +101,23 @@ void omap4_prm_vp_clear_txdone(u8 vp_id) OMAP4430_PRM_OCP_SOCKET_INST, vp->irqstatus_mpu); }; + +u32 omap4_prm_vcvp_read(u8 offset) +{ + return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, offset); +} + +void omap4_prm_vcvp_write(u32 val, u8 offset) +{ + omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, offset); +} + +u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +{ + return omap4_prminst_rmw_inst_reg_bits(mask, bits, + OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, + offset); +} diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index b28c87d..3d66ccd 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -755,6 +755,14 @@ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); u32 omap4_prm_vp_check_txdone(u8 vp_id); void omap4_prm_vp_clear_txdone(u8 vp_id); +/* + * OMAP4 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap4_prm_vcvp_read(u8 offset); +extern void omap4_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + # endif #endif