From patchwork Wed Sep 7 13:57:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 1127792 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p87GoTPZ016359 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 7 Sep 2011 16:50:50 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1IOV-0002dI-Im; Wed, 07 Sep 2011 13:42:25 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R1IOV-0002ey-3P; Wed, 07 Sep 2011 13:42:23 +0000 Received: from am1ehsobe003.messaging.microsoft.com ([213.199.154.206] helo=AM1EHSOBE003.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1INx-0002YP-Su for linux-arm-kernel@lists.infradead.org; Wed, 07 Sep 2011 13:41:52 +0000 Received: from mail96-am1-R.bigfish.com (10.3.201.249) by AM1EHSOBE003.bigfish.com (10.3.204.23) with Microsoft SMTP Server id 14.1.225.22; Wed, 7 Sep 2011 13:41:46 +0000 Received: from mail96-am1 (localhost.localdomain [127.0.0.1]) by mail96-am1-R.bigfish.com (Postfix) with ESMTP id 6D2D96C81CC; Wed, 7 Sep 2011 13:41:46 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzzz1202h1082kzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail96-am1 (localhost.localdomain [127.0.0.1]) by mail96-am1 (MessageSwitch) id 1315402906253982_16242; Wed, 7 Sep 2011 13:41:46 +0000 (UTC) Received: from AM1EHSMHS001.bigfish.com (unknown [10.3.201.252]) by mail96-am1.bigfish.com (Postfix) with ESMTP id 2F0C21430053; Wed, 7 Sep 2011 13:41:46 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS001.bigfish.com (10.3.207.101) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 7 Sep 2011 13:41:44 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.7; Wed, 7 Sep 2011 08:41:39 -0500 Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p87DfQAb020023; Wed, 7 Sep 2011 08:41:38 -0500 (CDT) From: Dong Aisheng To: Subject: [PATCH v2 3/3] arm: mxs: disable clock-gates when setting saif-clocks Date: Wed, 7 Sep 2011 21:57:38 +0800 Message-ID: <1315403858-9904-4-git-send-email-b29396@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1315403858-9904-1-git-send-email-b29396@freescale.com> References: <1315403858-9904-1-git-send-email-b29396@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110907_094150_419912_D6E8B64D X-CRM114-Status: GOOD ( 15.46 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.206 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, broonie@opensource.wolfsonmicro.com, lrg@ti.com, linux-arm-kernel@lists.infradead.org, w.sang@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 07 Sep 2011 16:50:50 +0000 (UTC) From: Wolfram Sang New divides should only be written when gates are off. Reported-by: Dong Aisheng Signed-off-by: Wolfram Sang --- Changes since v1: * Fix author name. It should be Wolfram Sang. :) BTW, i did a minus change based on wolfram's patch or the saif will not work. Change + __raw_writel(clkgate, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs##_SET); \ to + __raw_writel(reg & ~clkgate, \ CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ It seemed HW_CLKCTRL_##rs##_SET did not work well. (i did not find HW_CLKCTRL_SAIFx_SET in spec). --- arch/arm/mach-mxs/clock-mx28.c | 7 +++++-- arch/arm/mach-mxs/regs-clkctrl-mx28.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 33cc2ff..c9d0548 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -476,7 +476,7 @@ _CLK_SET_RATE1(xbus_clk, XBUS) static int name##_set_rate(struct clk *clk, unsigned long rate) \ { \ u16 div; \ - u32 reg; \ + u32 reg, clkgate; \ u64 lrate; \ unsigned long parent_rate; \ int i; \ @@ -493,7 +493,8 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ return -EINVAL; \ \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ - reg &= ~BM_CLKCTRL_##rs##_DIV; \ + clkgate = reg & BM_CLKCTRL_##rs##_CLKGATE; \ + reg &= ~(BM_CLKCTRL_##rs##_DIV | BM_CLKCTRL_##rs##_CLKGATE); \ reg |= div << BP_CLKCTRL_##rs##_DIV; \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ \ @@ -506,6 +507,8 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ return -ETIMEDOUT; \ } \ \ + __raw_writel(reg & ~clkgate, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ return 0; \ } diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h index 7d1b061..08749b3 100644 --- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h @@ -285,6 +285,7 @@ (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) #define HW_CLKCTRL_SAIF0 (0x00000100) +#define HW_CLKCTRL_SAIF0_SET (0x00000104) #define BP_CLKCTRL_SAIF0_CLKGATE 31 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 @@ -296,6 +297,7 @@ (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) #define HW_CLKCTRL_SAIF1 (0x00000110) +#define HW_CLKCTRL_SAIF1_SET (0x00000114) #define BP_CLKCTRL_SAIF1_CLKGATE 31 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000