From patchwork Wed Sep 7 16:03:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1127282 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p87G5CZa027684 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 7 Sep 2011 16:05:34 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1Kar-0000rK-Fr; Wed, 07 Sep 2011 16:03:19 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R1Kaq-0005Dm-TB; Wed, 07 Sep 2011 16:03:16 +0000 Received: from mail-ww0-f49.google.com ([74.125.82.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1Kan-0005Cq-Ma for linux-arm-kernel@lists.infradead.org; Wed, 07 Sep 2011 16:03:14 +0000 Received: by wwf10 with SMTP id 10so5164969wwf.18 for ; Wed, 07 Sep 2011 09:03:12 -0700 (PDT) Received: by 10.216.37.130 with SMTP id y2mr3609377wea.19.1315411392338; Wed, 07 Sep 2011 09:03:12 -0700 (PDT) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id fp17sm949265wbb.6.2011.09.07.09.03.10 (version=SSLv3 cipher=OTHER); Wed, 07 Sep 2011 09:03:11 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: Documentation: Update the Booting document with SMP boot advice Date: Wed, 7 Sep 2011 17:03:05 +0100 Message-Id: <1315411385-17669-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110907_120313_905831_B121CB0D X-CRM114-Status: GOOD ( 13.54 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 07 Sep 2011 16:05:34 +0000 (UTC) Currently, Booting doesn't say anything about booting on an SMP system. Although SMP boot varies somewhat from platform to platform, there are some general requirements which will usually apply. This patch documents those likely requirements, which should help to encourage some consistency between implementations. There's also some minor rearrangement of the text to restore a logical reading order after the other changes. Signed-off-by: Dave Martin --- Documentation/arm/Booting | 31 ++++++++++++++++++++----------- 1 files changed, 20 insertions(+), 11 deletions(-) diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index a341d87..dac6f02 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -146,22 +146,31 @@ In either case, the following conditions must be met: corrupted by bogus network packets or disk data. This will save you many hours of debug. -- CPU register settings +- Put the CPU(s) into the appropriate state. + On SMP systems, these requirements normally apply to all secondary + CPUs as well as the boot CPU. However, the exact requirements for + secondary CPUs may be platform-specific. + + - CPU mode + All forms of interrupts must be disabled (IRQs and FIQs) + The CPU must be in SVC mode. (A special exception exists for Angel) + + - Caches, MMUs + The MMU must be off. + Instruction cache may be on or off. + Data cache must be off. + + - For SMP platforms, put the secondary CPUs in the appropriate state + (such as entering a wait loop). The exact requirements depend on + the platform code. + +- Boot CPU register settings r0 = 0, r1 = machine type number discovered in (3) above. r2 = physical address of tagged list in system RAM, or physical address of device tree block (dtb) in system RAM -- CPU mode - All forms of interrupts must be disabled (IRQs and FIQs) - The CPU must be in SVC mode. (A special exception exists for Angel) - -- Caches, MMUs - The MMU must be off. - Instruction cache may be on or off. - Data cache must be off. - -- The boot loader is expected to call the kernel image by jumping +- Finally, the boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. On CPUs supporting the ARM instruction set, the entry must be