From patchwork Thu Sep 8 12:04:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Koyamangalath, Abhilash" X-Patchwork-Id: 1129452 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p88C5dAg011408 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 8 Sep 2011 12:06:01 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1dM2-0001yz-WA; Thu, 08 Sep 2011 12:05:17 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R1dM2-0004Ls-JJ; Thu, 08 Sep 2011 12:05:14 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1dLw-0004Ka-SG for linux-arm-kernel@lists.infradead.org; Thu, 08 Sep 2011 12:05:10 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p88C4vMT016517 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Sep 2011 07:04:59 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88C4v3q018166; Thu, 8 Sep 2011 17:34:57 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Thu, 8 Sep 2011 17:34:57 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88C4uSa021310; Thu, 8 Sep 2011 17:34:56 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p88C4uwj017584; Thu, 8 Sep 2011 17:34:56 +0530 Received: (from x0151633@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p88C4uRX017581; Thu, 8 Sep 2011 17:34:56 +0530 From: Abhilash K V To: Subject: [PATCH v3 2/2] omap_twl: Prevent SR to enable for am3517/am3505 devices Date: Thu, 8 Sep 2011 17:34:56 +0530 Message-ID: <1315483496-17547-1-git-send-email-abhilash.kv@ti.com> X-Mailer: git-send-email 1.6.2.4 MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110908_080509_079674_52B47A38 X-CRM114-Status: GOOD ( 13.77 ) X-Spam-Score: -2.8 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.40 listed in list.dnswl.org] -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, paul@pwsan.com, linux@arm.linux.org.uk, b-cousson@ti.com, tony@atomide.com, linux-kernel@vger.kernel.org, Vaibhav Hiremath , Abhilash K V , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 08 Sep 2011 12:06:01 +0000 (UTC) In case of AM3517 & AM3505, SmartReflex is not applicable so we must not enable it. So omap3_twl_init() is now not called when the processor does not support SR. This is as per discussion at http://marc.info/?l=linux-omap&m=131417482924928&w=2 Signed-off-by: Vaibhav Hiremath Signed-off-by: Abhilash K V --- arch/arm/mach-omap2/id.c | 2 +- arch/arm/mach-omap2/pm.c | 3 ++- arch/arm/plat-omap/include/plat/cpu.h | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37efb86..da71098 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -202,7 +202,7 @@ static void __init omap3_check_features(void) if (cpu_is_omap3630()) omap_features |= OMAP3_HAS_192MHZ_CLK; if (!cpu_is_omap3505() && !cpu_is_omap3517()) - omap_features |= OMAP3_HAS_IO_WAKEUP; + omap_features |= (OMAP3_HAS_IO_WAKEUP | OMAP3_HAS_SR); omap_features |= OMAP3_HAS_SDRC; diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 3feb359..8929798 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -254,7 +254,8 @@ postcore_initcall(omap2_common_pm_init); static int __init omap2_common_pm_late_init(void) { /* Init the OMAP TWL parameters */ - omap3_twl_init(); + if (omap3_has_sr()) + omap3_twl_init(); omap4_twl_init(); /* Init the voltage layer */ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 67b3d75..294e015 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -491,6 +491,7 @@ extern u32 omap_features; #define OMAP4_HAS_MPU_1GHZ BIT(8) #define OMAP4_HAS_MPU_1_2GHZ BIT(9) #define OMAP4_HAS_MPU_1_5GHZ BIT(10) +#define OMAP3_HAS_SR BIT(11) #define OMAP3_HAS_FEATURE(feat,flag) \ @@ -507,6 +508,7 @@ OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) OMAP3_HAS_FEATURE(sdrc, SDRC) +OMAP3_HAS_FEATURE(sr, SR) /* * Runtime detection of OMAP4 features