From patchwork Thu Sep 8 12:47:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Koyamangalath, Abhilash" X-Patchwork-Id: 1129532 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p88Clweb013189 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 8 Sep 2011 12:48:19 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1e12-0003O9-9k; Thu, 08 Sep 2011 12:47:38 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R1e11-0004ht-V3; Thu, 08 Sep 2011 12:47:35 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R1e0n-0004fF-VA for linux-arm-kernel@lists.infradead.org; Thu, 08 Sep 2011 12:47:23 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p88ClCkl015807 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Sep 2011 07:47:14 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88ClCUW024558; Thu, 8 Sep 2011 18:17:12 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Thu, 8 Sep 2011 18:17:12 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88ClBk0024390; Thu, 8 Sep 2011 18:17:11 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p88ClB8n000547; Thu, 8 Sep 2011 18:17:11 +0530 Received: (from x0151633@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p88ClBi2000543; Thu, 8 Sep 2011 18:17:11 +0530 From: Abhilash K V To: , , Subject: [PATCH v2 1/3] AM35x: voltage: Basic initialization Date: Thu, 8 Sep 2011 18:17:11 +0530 Message-ID: <1315486031-513-1-git-send-email-abhilash.kv@ti.com> X-Mailer: git-send-email 1.6.2.4 MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110908_084722_179740_03264052 X-CRM114-Status: GOOD ( 18.73 ) X-Spam-Score: -2.8 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [198.47.26.153 listed in list.dnswl.org] -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, linux@arm.linux.org.uk, sameo@linux.intel.com, tony@atomide.com, santosh.shilimkar@ti.com, Abhilash K V , premi@ti.com, david.woodhouse@intel.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 08 Sep 2011 12:48:19 +0000 (UTC) From: Sanjeev Premi This patch adds the basic initialization of voltage layer for AM35x. Since AM35x doesn't support voltage scaling, Many functions have been defined to plug into existing voltage layer. Signed-off-by: Sanjeev Premi Signed-off-by: Abhilash K V --- arch/arm/mach-omap2/omap_opp_data.h | 1 + arch/arm/mach-omap2/opp3xxx_data.c | 10 ++++++ arch/arm/mach-omap2/pm.c | 3 +- arch/arm/mach-omap2/voltage.c | 18 +++++++++++ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 41 ++++++++++++++++++++++++- 5 files changed, 71 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h index c784c12..c7cedf3 100644 --- a/arch/arm/mach-omap2/omap_opp_data.h +++ b/arch/arm/mach-omap2/omap_opp_data.h @@ -88,6 +88,7 @@ extern struct omap_volt_data omap34xx_vddmpu_volt_data[]; extern struct omap_volt_data omap34xx_vddcore_volt_data[]; extern struct omap_volt_data omap36xx_vddmpu_volt_data[]; extern struct omap_volt_data omap36xx_vddcore_volt_data[]; +extern struct omap_volt_data am35xx_vdd_volt_data[]; extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[]; extern struct omap_volt_data omap44xx_vdd_iva_volt_data[]; diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index d95f3f9..2337d0f 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -150,6 +150,16 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV), }; +/* AM35x + * + * Fields related to SmartReflex and Voltage Processor are set to 0. + */ +struct omap_volt_data am35xx_vdd_volt_data[] = { + VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, 0x0, 0x0, 0x0), + VOLT_DATA_DEFINE(0, 0, 0, 0), +}; + + /** * omap3_opp_init() - initialize omap3 opp table */ diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 8929798..863b384 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -227,7 +227,8 @@ static void __init omap3_init_voltages(void) { if (!cpu_is_omap34xx()) return; - + if (cpu_is_omap3505() || cpu_is_omap3517()) + return; omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev); omap2_set_init_voltage("core", "l3_ick", l3_dev); } diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 9ef3789..3fa0652 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -60,6 +60,12 @@ static struct dentry *voltage_dir; static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd, unsigned long target_volt); +static int volt_scale_nop(struct omap_vdd_info *vdd, + unsigned long target_volt) +{ + return 0; +} + static u32 omap3_voltage_read_reg(u16 mod, u8 offset) { return omap2_prm_read_mod_reg(mod, offset); @@ -114,6 +120,12 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd) sys_clk_speed /= 1000; /* Generic voltage parameters */ + if (cpu_is_omap3505() || cpu_is_omap3517()) { + vdd->volt_scale = volt_scale_nop; + vdd->vp_enabled = false; + return 0; + } + vdd->volt_scale = vp_forceupdate_scale_voltage; vdd->vp_enabled = false; @@ -217,6 +229,9 @@ static void __init vp_init(struct omap_vdd_info *vdd) { u32 vp_val; + if (cpu_is_omap3505() || cpu_is_omap3517()) + return ; + if (!vdd->read_reg || !vdd->write_reg) { pr_err("%s: No read/write API for accessing vdd_%s regs\n", __func__, vdd->voltdm.name); @@ -598,6 +613,9 @@ static void __init omap_vc_init(struct omap_vdd_info *vdd) { u32 vc_val; + if (cpu_is_omap3505() || cpu_is_omap3517()) + return ; + if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { pr_err("%s: PMIC info requried to configure vc for" "vdd_%s not populated.Hence cannot initialize vc\n", diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index def230f..7432a1b 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -67,6 +67,39 @@ static struct omap_vdd_info *omap3_vdd_info[] = { &omap3_vdd2_info, }; +/* + * AM35x VDD structures + * + * In AM35x there neither scalable voltage domain nor any hook-up with + * voltage controller/processor. However, when trying to re-use the hwmod + * database for OMAP3, definition of "core" voltage domain is necessary. + * Else, changes in hwmod data structures grow spirally. + * + * As a workaround, "core" voltage domain is defined below. This is an ad hoc + * arrangement till code for SoCs without scalable voltage domains gets + * an overhaul. + */ +static struct omap_vdd_info am3517_vdd1_info = { + .vp_enabled = false, + + .voltdm = { + .name = "mpu", + }, +}; + +static struct omap_vdd_info am3517_vdd2_info = { + .vp_enabled = false, + + .voltdm = { + .name = "core", + }, +}; + +static struct omap_vdd_info *am3517_vdd_info[] = { + &am3517_vdd1_info, + &am3517_vdd2_info, +}; + /* OMAP3 specific voltage init functions */ static int __init omap3xxx_voltage_early_init(void) { @@ -80,7 +113,13 @@ static int __init omap3xxx_voltage_early_init(void) * XXX Will depend on the process, validation, and binning * for the currently-running IC */ - if (cpu_is_omap3630()) { + if (cpu_is_omap3505() || cpu_is_omap3517()) { + am3517_vdd1_info.volt_data = am35xx_vdd_volt_data; + am3517_vdd2_info.volt_data = am35xx_vdd_volt_data; + return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod, + am3517_vdd_info, + ARRAY_SIZE(am3517_vdd_info)); + } else if (cpu_is_omap3630()) { omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data; omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data; } else {