From patchwork Fri Jul 6 18:40:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 1167021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 0FFBD3FC33 for ; Fri, 6 Jul 2012 19:01:25 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SnDc0-0007VC-IA; Fri, 06 Jul 2012 18:50:40 +0000 Received: from mail-ob0-f177.google.com ([209.85.214.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SnDSv-0005Jd-F4 for linux-arm-kernel@lists.infradead.org; Fri, 06 Jul 2012 18:41:29 +0000 Received: by mail-ob0-f177.google.com with SMTP id ta17so15691949obb.36 for ; Fri, 06 Jul 2012 11:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Pym1zRMXRoS08wi8Hrq3N8W0+5SoueRYSNm3wdNQIy8=; b=RPf+di7N0yXh66vFKv9YSuIrDLDffC4wISrs7/oOPRXNf81eDca63LPUzf9dJuwJlJ v2EUrHMT+0itMiSb3T7/JxrVGs+WRVmbqLv4Pto/PpKyWWL8ob3xoS5Pys+pg7ahtoaJ Jd2bc+Zc9LQBGhKz54p1OccxVr8agHxwpx2iM7RsrBLmpmZP5q1fLdGVNaPSVr1OUCos JrnAtazH71u5O1cTD+qjKoMvsucmcSArM3VbhUthL80nTaxPW84nnm6FHr4LIbdXWl0l Nl5BySNy+QzV1/McwLL0a5EgbnTOoMs+NB0gf3UuiNSVDokncgTKsleRibZ231bVMSOz nz2w== Received: by 10.60.172.236 with SMTP id bf12mr28106623oec.23.1341600077128; Fri, 06 Jul 2012 11:41:17 -0700 (PDT) Received: from rob-laptop.calxeda.com ([173.226.190.126]) by mx.google.com with ESMTPS id u5sm23928763obk.2.2012.07.06.11.41.14 (version=SSLv3 cipher=OTHER); Fri, 06 Jul 2012 11:41:15 -0700 (PDT) From: Rob Herring To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/15] ARM: mv78xx0: use fixed pci i/o mapping Date: Fri, 6 Jul 2012 13:40:37 -0500 Message-Id: <1341600040-30993-13-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341600040-30993-1-git-send-email-robherring2@gmail.com> References: <1341600040-30993-1-git-send-email-robherring2@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (robherring2[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Andrew Lunn , Stephen Warren , Jason Cooper , Arnd Bergmann , Nicolas Pitre , thierry.reding@avionic-design.de, Rob Herring , bhelgaas@google.com, Colin Cross , Olof Johansson , Russell King X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Rob Herring Move mv78xx0 PCI to fixed i/o mapping and remove io.h. This changes the PCI bus addresses from the cpu address to 0 based. It appears that there is translation h/w for this, but its untested. Signed-off-by: Rob Herring Cc: Jason Cooper Cc: Andrew Lunn --- arch/arm/Kconfig | 1 - arch/arm/mach-mv78xx0/addr-map.c | 1 + arch/arm/mach-mv78xx0/common.c | 18 ++++++++++++----- arch/arm/mach-mv78xx0/include/mach/io.h | 24 ---------------------- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 22 +++++++++----------- arch/arm/mach-mv78xx0/pcie.c | 28 +++++--------------------- 6 files changed, 29 insertions(+), 65 deletions(-) delete mode 100644 arch/arm/mach-mv78xx0/include/mach/io.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c61e0a4..1b7faa5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -571,7 +571,6 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 62b53d7..da9806a 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "common.h" /* diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b4c53b8..e018d8c 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -135,11 +136,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, - }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, @@ -150,6 +146,18 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { void __init mv78xx0_map_io(void) { unsigned long phys; + unsigned long pci_io_pfn[] = { + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(1)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(2)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(3)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(4)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(5)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(6)), + __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(7)), + }; + + pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn), SZ_64K); /* * Map the right set of per-core registers depending on diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00..0000000 --- a/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c..10fc138 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,11 +46,9 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE 0xfd000000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86..a51a1e4 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "common.h" struct pcie_port { @@ -30,9 +31,6 @@ struct pcie_port { static struct pcie_port pcie_port[8]; static int num_pcie_ports; -static struct resource pcie_io_space; -static struct resource pcie_mem_space; - void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -47,22 +45,6 @@ static void __init mv78xx0_pcie_preinit(void) u32 start; int win; - pcie_io_space.name = "PCIe I/O Space"; - pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); - pcie_io_space.end = - MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; - if (request_resource(&iomem_resource, &pcie_io_space)) - panic("can't allocate PCIe I/O space"); - - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); - for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; @@ -70,8 +52,8 @@ static void __init mv78xx0_pcie_preinit(void) "PCIe %d.%d I/O", pp->maj, pp->min); pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; + pp->res[0].start = i * SZ_64K; + pp->res[0].end = pp->res[0].start + SZ_64K - 1; pp->res[0].flags = IORESOURCE_IO; snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), @@ -118,10 +100,10 @@ static void __init mv78xx0_pcie_preinit(void) for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - if (request_resource(&pcie_io_space, &pp->res[0])) + if (request_resource(&ioport_resource, &pp->res[0])) panic("can't allocate PCIe I/O sub-space"); - if (request_resource(&pcie_mem_space, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res[1])) panic("can't allocate PCIe MEM sub-space"); }